On-chip power consumption management method, electronic device and storage medium

A power consumption management method and power consumption technology, which is applied in data processing power supply, electrical digital data processing, measurement flow/mass flow, etc., can solve problems such as abnormal chip operation, achieve control of chip abnormality, improve chip power supply integrity, The effect of active power control

Active Publication Date: 2022-03-15
上海燧原科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The voltage drop is likely to cause problems such as abnormal operation of the chip

Method used

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  • On-chip power consumption management method, electronic device and storage medium
  • On-chip power consumption management method, electronic device and storage medium
  • On-chip power consumption management method, electronic device and storage medium

Examples

Experimental program
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Embodiment 1

[0023] figure 2 The flow chart of the on-chip power consumption management method provided by Embodiment 1 of the present invention, this embodiment is applicable to the situation of controlling chip power consumption, this method can be executed by electronic equipment with large-scale integrated circuits, and the electronic equipment can For smart terminals, personal computers, tablet computers or notebook computers, etc., specifically include the following steps:

[0024] Step 110, acquiring first power consumption prediction information of instructions of multiple single cores within the prediction window.

[0025] Each single core sequentially reads and executes instructions according to the clock cycle. Instructions within the prediction window are unexecuted instructions on a single core. The length of the prediction window can be multiple clock cycles. Instructions to be executed within the prediction window can be obtained from unexecuted codes according to the av...

Embodiment 2

[0067] image 3 The flow chart of the on-chip power consumption management method provided by Embodiment 2 of the present invention serves as a specific description of the foregoing implementation manner. Wherein, step 110, obtaining the first power consumption prediction information of instructions of multiple single cores within the prediction window may be implemented as: obtaining instructions of multiple single cores within the prediction window; obtaining the prediction window according to the power consumption information of the instructions The maximum power consumption and the minimum power consumption within. Step 130, determining the second warning information according to multiple first power consumption prediction information of multiple single cores, may be implemented as: accumulating the maximum power consumption and minimum power consumption of multiple single cores; The maximum value and the accumulated minimum value of power consumption determine the power ...

Embodiment 3

[0082] Figure 4The flow chart of the on-chip power consumption management method provided by Embodiment 3 of the present invention serves as a specific description of the foregoing implementation manner. Wherein, step 110, obtaining the first power consumption prediction information of instructions of multiple single cores within the prediction window may be implemented as: obtaining instructions of multiple single cores within the prediction window; obtaining the prediction window according to the power consumption information of the instructions The average power consumption within. Step 130, determining the second warning information according to multiple first power consumption prediction information of multiple single cores, may be implemented as: accumulating the average power consumption; judging whether the power supply is sufficient according to the accumulated average power consumption; If it is not enough, the content of the second warning message is a warning. T...

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Abstract

The invention discloses an on-chip power consumption management method, an electronic device and a storage medium, comprising: acquiring first power consumption prediction information of instructions of multiple single cores within a prediction window; single cores according to the local first power consumption prediction information Determine the first warning information; determine the second warning information and power consumption control information according to multiple first power consumption prediction information of multiple single cores; if both the first warning information and the second warning information are warnings, then sequentially Power consumption control is carried out in the core, and resource interaction is carried out with the subsystem controller according to the power consumption control information. It is possible to control the power consumption in advance before the voltage abnormality occurs through the predictive method, and the power consumption control can be performed in advance before the abnormality occurs, and the abnormality of the chip can be effectively controlled. In a multi-core scenario, while performing power consumption control in the single-core local area, the resource interaction between the subsystem controller and the single-core local area can be performed more effectively to control the power consumption of the single-core local area and improve chip power integrity. .

Description

technical field [0001] Embodiments of the present invention relate to chip control technology, and in particular to an on-chip power consumption management method, electronic equipment and storage media. Background technique [0002] With the improvement of integrated circuit manufacturing technology, the computing power density of chips increases accordingly. With the increase of the computing power density of the chip, the power integrity requirements of the chip are getting higher and higher. [0003] At present, during the operation of the chip, there will be a large current change in the chip in a short period of time. For example, a current change of several hundreds of amperes occurs in a short time of nanosecond order. This will cause a large voltage drop (VoltageOvershoot) in the chip voltage. The voltage drop is likely to cause problems such as abnormal operation of the chip. [0004] How to effectively control chip abnormalities has become an urgent problem to...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/30G06F11/32G06F1/26
CPCG06F11/3062G06F11/327G06F1/26Y02D10/00
Inventor 陈教彦鲍敏祺陈亮
Owner 上海燧原科技有限公司
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