A fishbone clock tree and its implementation method

Abstract

The invention belongs to the technical field of clock trees, and discloses a fishbone clock tree and an implementation method. The fishbone clock tree includes a main clock tree and several sub clock trees, the main clock tree is derived from a PLL, and the sub clock trees are The clock tree is derived from the main clock tree, and the sub-clock tree is provided with several clock bifurcation points, and the clock bifurcation points serve as the source of the traditional clock tree to establish the traditional clock tree. The beneficial effect is that: the fishbone clock tree structure is established by establishing the main clock tree and the sub-clock tree, which reduces the buffer unit between the PLL and the chip sub-module, and reduces the power consumption of the chip; the main clock tree and the sub-clock tree also serve as a common path The effect of OCV is less clock cycle, and the final timing convergence is easy.

Description

technical field [0001] The invention relates to the technical field of clock trees, in particular to a fishbone-shaped clock tree and an implementation method. Background technique [0002] The clock tree is a mesh structure balanced by many buffer cells (buffer / inv cells). It has a source point, which is usually the clock input port (clock input port), or it may be a cell output pin (cell) inside the design. output pin), which is built from level-by-level buffer units. The key factors for measuring the quality of the clock tree include: the length of the clock tree, the common path of the clock tree, the clock tree signal transition time (clock transition time), and the clock tree drift (clock tree drift). skew), clock tree noise, clock duty cycle. [0003] The clock tree construction scheme is a very important step in the realization of the back-end physical design of the chip. The quality of the clock tree is directly related to the power consumption of the chip and the ...

AI Technical Summary

Problems solved by technology

[0005] Those skilled in the art know that too many clock buffers will cause the length of the clock tree to be long, the power consumption of the clock tree will be large, and it will easily cause channel wiring congestion, the clock tree wiring will take up more resources, and the noise on the clock tree will be large. Too many will also cause the clock tree to bifurcate early and the common path will be less, and the clock cycle occupied by OCV will be more, and the final timing convergence will be difficult

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