A Method for FPGA Accelerated Realization of Singular Value Decomposition of Matrix

Abstract

The invention discloses an FPGA accelerated implementation method of singular value decomposition of a matrix. The method firstly divides a matrix of m rows×n columns stored in an off-chip DRAM into p=n / k sub-blocks according to a group of k column vectors. , the p sub-blocks are alternately combined in pairs in order to obtain a small-sized matrix of m rows × 2k columns and write it into the internal BRAM of the FPGA, and further perform unilateral Jacobi rotation transformation, and half of the column vectors in the obtained calculation results are written back to the slice Outside the DRAM, the other half of the column vectors will continue to be combined with the next sub-block to obtain a new m-row×2k-column matrix, and the above operations will be repeated on the FPGA, until p sub-blocks are combined in pairs to perform a full round of unilateral Jacobi rotation Transformation; perform the above operations multiple times until the convergence condition is satisfied, that is, the singular value decomposition of the large-size matrix with m rows×n columns is completed. The present invention adopts a divide-and-conquer decomposition strategy and an implementation mode of alternate combination between sub-blocks, which improves the data multiplexing rate, reduces frequent data transfer, and reduces the bandwidth pressure of on-chip and off-chip data transmission.

Description

technical field [0001] The invention relates to the field of signal processing, in particular to an FPGA accelerated realization method of matrix singular value decomposition. Background technique [0002] Singular value decomposition is an important matrix decomposition in linear algebra, which is widely used in signal processing, image compression and deep learning. In the current existing research, it is mainly implemented by CPU or GPU in the form of software programs. In recent years, with the rapid development of FPGA technology, the use of FPGA to realize matrix singular value decomposition has gradually become a popular technology, especially some FPGAs that have deployed In the application scenario, implementing matrix singular value decomposition based on FPGA to replace the GPU solution can reduce costs and reduce power consumption. Compared with the CPU solution, it can obtain more real-time and low-latency performance. [0003] However, singular value decomposi...

AI Technical Summary

Problems solved by technology

[0003] However, singular value decomposition involves a large number of mathematical operations and loop iterations, especially for large-scale matrices, which are computationally intensive and storage-intensive. Both put forward harsh requirements, but also lead to the extremely difficult and huge workload of FPGA development

In the published research and inventions, due to the limited FPGA resources and the high complexity of the singular value decomposition itself, the matrix size of the current singular value decomposition based on the FPGA is generally small, the real-time performance is poor, and it can only support fixed-size Insufficient matrix input etc.

Images