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Semiconductor structure and preparation method thereof

A semiconductor and deposition method technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc., can solve problems such as poor capacitance hole devices

Pending Publication Date: 2021-10-19
INST OF MICROELECTRONICS CHINESE ACAD OF SCI +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] The first object of the present invention is to provide a semiconductor structure containing a capacitor hole, the capacitor hole of the structure has a good shape, which solves the problem of defective devices in the prior art due to the poor shape of the capacitor hole

Method used

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  • Semiconductor structure and preparation method thereof
  • Semiconductor structure and preparation method thereof
  • Semiconductor structure and preparation method thereof

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Embodiment Construction

[0025] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

[0026] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions / layers with different shapes, ...

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Abstract

The invention relates to a semiconductor structure and a preparation method thereof. A semiconductor structure containing a capacitor hole comprises the capacitor hole, and an etching stop layer of the capacitor hole is composed of at least two layers of nitride films. The densities of the two layers of nitride films are different; in order to enable the densities of the at least two layers of nitride films to be different, an in-situ deposition mode is adopted. The invention relates to a preparation method of a semiconductor structure, which comprises the following steps that an etching stop layer is deposited on a semiconductor substrate, and a capacitor hole is formed through a subsequent process. The method for depositing the etching stop layer is as follows: a plurality of layers of nitride films are deposited on the semiconductor substrate, the plurality of layers of nitride films are sequentially stacked up and down, and the deposition methods adopted by the plurality of layers of nitride films are different. The problem of poor device caused by poor appearance of the capacitance hole in the prior art is solved.

Description

technical field [0001] The invention relates to the field of semiconductor preparation, in particular to a semiconductor structure and a preparation method thereof. Background technique [0002] In the preparation of semiconductor capacitors, the morphology of the capacitor contact is particularly important to the quality of the device. Capacitor holes are etched on the multi-layer stacks that have been formed on the substrate. As the etching goes deeper, the critical dimension of the holes becomes narrower, which is very detrimental to the electrical characteristics of the device, especially the bottom etching stop layer (Etching stopper) has a significant impact on the shape of the capacitor hole, so how to improve the narrowing of the capacitor hole at the bottom is very important to improve the quality of the device. Contents of the invention [0003] The first object of the present invention is to provide a semiconductor structure containing a capacitor hole. The cap...

Claims

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Application Information

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IPC IPC(8): H01L27/108H01L21/8242
CPCH10B12/01H10B12/00
Inventor 李相遇安重镒金成基熊文娟李亭亭杨涛李俊峰王文武
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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