Multi-core starting method based on shared space

Abstract

The invention discloses a multi-core starting method based on a shared space. The method comprises the following steps of: using an FPGA, hooking the FPGA in an IO space of a core 1, simultaneously hooking the FPGA in CE1 starting FLASH spaces of a core 2, a core 3 and a core 4; simulating the CE1 starting spaces of the cores 2, 3 and 4 through the FPGA, moving a starting program of the core 2 in the FLASH of the core 1 to a shared memory space of the FPGA after starting the core 1; releasing reset of the core 2, making the core 2 to start guide software; making the guide software of the core 2 interact with the core 1; moving application software to the internal RAM space of the FPGA through the shared space of the FPGA;starting the application software to run the application software; and implementing the starting process of the core 3 and the starting process of the core 4 as the above steps. According to the method, hardware cost and size are saved; and in addition, a three-bus interaction control mode of a processor is used. The method has the advantages of good universality, convenient transplantation, low software development cost and higher practical application value.

Description

technical field [0001] The invention belongs to the field of software starting methods, and in particular relates to a multi-core starting method based on a shared space. Background technique [0002] With the continuous development of processor integration technology, high-performance and highly integrated multi-core processors have been widely used. In the past, multiple computers can be integrated into one computer, and multi-core processors can be used instead of the original multiple computers to process different tasks. program. However, some multi-core processors only integrate processors, and each processor still needs to configure the boot memory separately, as in figure 1 shown. Usually, the startup program of an embedded computer takes up relatively little space, and the startup memory space is wasted a lot. On the other hand, military or aerospace memory has a large volume and high cost, which hinders the further improvement of computer system integration and ...

AI Technical Summary

Problems solved by technology

However, some multi-core processors only integrate processors, and each processor still needs to configure the boot memory separately, as in figure 1 shown

Usually, the startup program of an embedded computer occupies a relatively small space, and the startup memory space is wasted a lot

On the other hand, military or aerospace memory is bulky and expensive, which hinders the further improvement of computer system integration and cost reduction design.

[0003] DSP6713J / 500 is a 4-core high-performance and high-reliability military processor. The processor currently supports two multi-core startup methods. One is the ROM startup method, which needs to be connected to a FLASH for each core. The core starts from the FLASH on the chip select CE1 memory. The second startup method is to use HPI to start. HPI startup requires two conditions. First, the processor must have an HPI interface, and second, add an FPGA outside the chip to simulate the HPI host through the FPGA. The host function starts multi-core through the HPI controller inside the FPGA. This method cannot be used for processors without an HPI interface. Therefore, the HPI method is only applicable to specific processors and does not have the conditions for widespread application.

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