Global layout method for 2.5D packaged FPGA

Abstract

The invention relates to a global layout method for a 2.5D packaged FPGA, and the method comprises the following steps: defining a line length constraint condition through a line length estimation function, constraining a super-long line SLL through a penalty cost function, processing clock constraint through a clock fence area cost function, constraining module distribution through a three-dimensional module distribution cost function based on a 3D Poisson equation, expressing the global layout method of the 2.5D packaged FPGA as an unconstrained optimization problem including a line length estimation function, a penalty cost function, a clock fence area cost function and a three-dimensional module distribution cost function, expressing the unconstrained optimization problem as a separable optimization problem with linear constraints, and solving the separable optimization problem by adopting a near-end group domain ADMM; and carrying out detailed layout by using clock constraint legalization so as to realize layout legalization. According to the global layout method, layout calculation time is shortened, super-long lines are remarkably reduced on a base layer meeting clock constraint and line length constraint, and a more effective legalized layout result is obtained.

Description

technical field [0001] The invention relates to the technical field of VLSI physical design automation, in particular to a global layout method for 2.5D packaging FPGA. Background technique [0002] A Field Programmable Gate Array (FPGA) is a prefabricated integrated circuit that can be customized in the field. FPGAs are widely used in circuit implementation due to their higher flexibility compared to conventional (ASICs) and the ability to be reprogrammed in the field according to design changes, reducing time-to-market and non-recurring engineering costs . With significant enhancements to modern FPGA architectures, high-performance large-scale FPGAs can accommodate up to millions of logic gates, and thousands of heterogeneous blocks, including random access memories (RAMs), digital signal processors (DSPs) and intelligent components (IPs). For example, Xilinx 2.5D FPGAs, such as the Virtex-7 and Virtex Ultrascale families, are commercially available. With the continuou...

AI Technical Summary

Problems solved by technology

[0005] Existing global placement methods for 2.5D FPGAs suffer from the following problems: critical SLL issues and special clock constraints are considered separately, which may lead to timing violations or routing failures

Images