SHA-less pipeline ADC sampling time error calibration system and method

Abstract

The invention discloses an SHA-less pipeline ADC sampling time error calibration system, and belongs to the field of analog-to-digital conversion. The system comprises a clock generation module, N pipeline level modules, a digital code dislocation addition module and an error calibration module, wherein the error calibration module comprises an error detection unit and a delay line calibration unit. The invention also provides a corresponding calibration method, the error detection unit detects the residual error output result of the first pipeline stage and generates a control signal to control the delay of the delay line calibration unit, so as to adjust the sampling time of the sub-ADC. And through multiple iterations, the sampling time of the sub-ADC is aligned with the sampling time of the MDAC, and calibration is completed. Once the sampling time deviates due to the change of the external environment, the calibration module is activated again immediately. The calibration method provided by the invention is high in calibration precision, and can have higher calibration precision and shorter calibration time for high-frequency analog signals.

Description

technical field [0001] The invention relates to the technical field of analog-to-digital conversion, in particular to a SHA-less pipeline ADC sampling time error calibration system and method. Background technique [0002] In recent years, with the development of social information technology, the requirements for high-speed and high-precision ADCs are getting higher and higher in the fields of wireless communication, high-precision instrumentation and information transmission. Pipeline ADC has a good compromise in terms of speed, precision and power consumption, so it is widely used in high-speed and high-precision occasions. [0003] Existing studies have shown that the use of no front-end sample-and-hold (SHA-less) circuit is the pipeline structure with the lowest power consumption. However, the SHA-less pipeline ADC has an inherent shortcoming, which is the sampling time deviation between the sampling circuit of the sub-ADC and the sampling circuit of the MDAC. This is...

AI Technical Summary

Problems solved by technology

However, this detection method can only detect whether there is an error voltage, but cannot detect the magnitude of the error voltage, that is, the detection accuracy and calibration speed are limited.

Images