Preparation method of three-dimensional memory

Abstract

The present application provides a method for preparing a three-dimensional memory, the method comprising: alternately stacking sacrificial layers and dielectric layers on one side of a substrate to form a stacked structure; a gate line gap; removing the sacrificial layer to form a gate gap; forming a deposition layer on an inner wall of the gate line gap and an inner wall of the gate gap; and alternately performing a dry etching process and a wet etching process to remove the deposition layer At least a portion of the gate gap to form a groove having a target depth at the gate gap.

Description

Preparation method of three-dimensional memory technical field [0001] The present application relates to the field of semiconductor manufacturing, and more particularly, to a method for preparing a three-dimensional memory. Background technique [0002] To overcome the limitations of two-dimensional (2D) memory devices, three-dimensional (3D) arrangement of memory cells on a substrate is currently to increase the integration density. Existing 3D NAND memory architectures typically have gate gaps arranged vertically and horizontally arranged Design of the metal gate layer. Common fabrication processes for 3D NAND memory include: forming a gate structure between insulating layers, Wherein, the gate structure sequentially includes a barrier layer and a metal tungsten layer from the inside to the outside; then the metal tungsten layer is etched to obtain a metal gate Floor. For example, the metal tungsten layer may be etched using wet etching or dry etching. [0003] Th...

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Problems solved by technology

The increased thickness of the deposited layer and the smaller critical dimensions lead to the side-capping of the bottom of the gate layer after the deposition process, resulting in tungsten residue after etch

Residual tungsten may affect the threshold voltage of the bottom selection gate and cause leakage current, and the residual tungsten also prevents the formation of silicon grooves during sidewall etching, which affects the final electrical performance

[0004] In the prior art, when the metal tungsten layer is directly etched by wet etching, the width of the bottom and top of the metal tungsten in the channel after etching is not uniform, that is, the RECESS GAP is very large, unable to meet production requirements

However, when dry etching is used to etch the metal tungsten layer, due to the anisotropy of dry etching, the metal tungsten deposited on the bottom sidewall of the gate line gap cannot be completely removed.

At this time, it is usually necessary to increase the intensity of dry etching to remove tungsten residues. However, too strong dry etching will cause the opening of the silicon groove to be damaged and enlarged, which will cause the oxidation of the opening at the subsequent filling of silicon oxide. Silicon layer is too thick

An overly thick silicon oxide layer will make it difficult to drill holes in the subsequent process that requires opening holes for circuit outreach.

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