Clock crossing FIFO status converged synchornizer

Abstract

The invention relates to a clock crossing FIFO status converged synchronizer. The synchronizer that can generate pipeline (e.g., FIFO, LIFO) status in a single step without intermediate synchronization. The status can be an indicator of whether a pipeline is full, empty, almost full, or almost empty. The synchronizer (also referred to as a double-sync or ripple-based pipeline status synchronizer) can be used with any kind of clock crossing pipeline and all kinds of pointer encoding. The double-sync and ripple-based pipeline status synchronizers eliminate costly validation and semi-manual timing closure, suggests better performance and testability, and have lower area and power.

Description

[0001] priority statement [0002] This application claims priority to U.S. Provisional Patent Application Serial No. 62 / 940,729, entitled "Clock Crossing FIFO Status Converged Synchronizer," filed November 26, 2019, in its entirety The contents are hereby incorporated by reference. technical field [0003] The present disclosure generally relates to clock crossing FIFO state convergence synchronizers. Background technique [0004] Currently, clock interleaved First-in-First-out (FIFO) cannot efficiently and directly generate convergent full, empty, almost full and / or almost empty states of the FIFO. Contents of the invention [0005] According to a first aspect of an embodiment of the present disclosure, there is provided an apparatus, including: a pipeline; a first set of pointers associated with the pipeline, wherein the first set of pointers is related to the set of pointers used to read from the pipeline A read clock is associated; a second set of pointers is assoc...

AI Technical Summary

Problems solved by technology

[0004] Currently, clock interleaved First-in-First-out (FIFO) cannot effectively directly generate the converged full, empty, almost full and / or almost empty states of the FIFO

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