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Low-power-consumption FPGA (Field Programmable Gate Array) partially reconfigurable method and low-power-consumption FPGA partially reconfigurable device

A low-power, reconfigurable system technology, applied in the architecture with a single central processing unit, digital computer components, digital data processing components, etc., can solve the problem of reconfigurable and ineffective power consumption, and avoid heat dissipation and stability issues, the effect of reducing ineffective power consumption

Pending Publication Date: 2021-04-02
INST OF COMPUTING TECH CHINESE ACAD OF SCI
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AI Technical Summary

Problems solved by technology

[0010] The purpose of the invention is to solve the problem of too much reconfigurable invalid power consumption of the FPGA part existing in the prior art

Method used

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  • Low-power-consumption FPGA (Field Programmable Gate Array) partially reconfigurable method and low-power-consumption FPGA partially reconfigurable device
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  • Low-power-consumption FPGA (Field Programmable Gate Array) partially reconfigurable method and low-power-consumption FPGA partially reconfigurable device

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Embodiment Construction

[0033]The inventor analyzed the configuration scheme of the static logic area and the dynamic logic area, and the composition of the power consumption of the static area, and proposed that the reduction of ineffective power consumption can be solved from two aspects:

[0034] The first aspect is to dynamically reduce the clock frequency of the logic in the static area to reduce the dynamic power consumption of the circuit caused by unnecessary high operating frequency, that is, to replace the static clock in the current industry solution by setting a dynamically reconfigurable clock unit Unit, which dynamically adjusts the clock of the CPU in the static logic area to reduce its power consumption in the idle state;

[0035] The second aspect is to flexibly reduce the idle power consumption of the external controller interface in the logic of the static area. According to the way the cloud service is provided, it is divided into two types of sub-scenarios:

[0036] In the scena...

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Abstract

The invention provides a low-power-consumption FPGA (Field Programmable Gate Array) partially reconfigurable method and a low-power-consumption FPGA partially reconfigurable device. According to the method and device provided by the scheme of the invention, the invalid power consumption of the FPGA static logic region is effectively reduced by combining the logic cutting and reconstruction switching technology of the FPGA static logic region and the clock frequency real-time adjustment mechanism of the memory control interface dormancy and dynamic clock management unit; and meanwhile, the problems of heat dissipation and stability caused by long-term working of the static logic region in a high-frequency state are further avoided.

Description

technical field [0001] The invention relates to the field of reconfigurable computing, and in particular to a low power consumption FPGA part reconfigurable method and device. Background technique [0002] The system structure of a computer has a crucial influence on its information processing ability. However, it is difficult to have a general computing architecture that is the optimal solution for all computing tasks. For example, in scenarios such as machine learning, databases, image processing, communications, and financial computing, computing tasks with different attributes have their own appropriate computing architectures, which often require the design of dedicated custom chip architectures to obtain the best performance. Due to the high R&D cost and long production cycle of dedicated computing chips, the industry has been exploring how to use more flexible solutions to solve this problem in recent years. [0003] The idea of ​​reconfigurable computing originated...

Claims

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Application Information

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IPC IPC(8): G06F15/78G06F1/3234G06F1/324
CPCG06F15/7871G06F1/3234G06F1/324Y02D10/00
Inventor 张科齐乐陈明宇
Owner INST OF COMPUTING TECH CHINESE ACAD OF SCI
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