Hardware algorithm model construction method based on SysML

Abstract

The invention discloses a hardware algorithm model construction method based on SysML, and relates to the technical field of modeling simulation. The method comprises the following steps: establishinga module definition graph and an internal module graph of a hardware algorithm through SysML; storing the module definition graph and the internal module graph as a first text, and determining corresponding relationships between the module definition graph and the first text and between the internal module graph and the first text; extracting a first text by using a KMP algorithm and determininga mapping rule of the first text and the VHDL meta-model; and calling the VHDL meta-model, and converting the first text into a second text of the VHDL language according to the mapping rule. According to the method, the model is converted into the VHDL language for hardware algorithm model construction, the hardware modeling efficiency is improved, the problem that various models are difficult tounify in the complex product modeling process is solved, and the method is simple, convenient and easy to implement.

Description

technical field [0001] The invention relates to the technical field of modeling and simulation, and more specifically relates to a method for constructing a hardware algorithm model based on SysML. Background technique [0002] In the process of building the hardware circuit model, VHDL is generally used to describe the digital circuit logic. Ultra-high-speed integrated circuit hardware description language was born in 1982. It was originally a hardware description language proposed by the U.S. Department of Defense for its ultra-high-speed integrated circuit research program. Others can easily understand the design of the circuit. However, the VHDL syntax is complicated and difficult to understand, and it needs professionals with relevant experience in circuit design to design. However, for the hardware kernelization requirements of complex algorithms, many algorithm professionals do not understand VHDL, and hardware professionals do not understand algorithms. [0003] W...

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Problems solved by technology

[0004] In view of this, the present invention provides a hardware algorithm model construction method based on SysML to solve the problem that various models are difficult to unify in the modeling process of complex products, so that people who are not familiar with hardware modeling languages ​​can quickly build hardware circuit models

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