Cross-board-level homologous clock system

Abstract

The invention discloses a cross-board-level homologous clock system, which is characterized in that when multiple boards are stacked for use, a single board is defined as a main board, other single boards are defined as slave boards, a control module of the main board collects the frequency and phase of a clock signal fed back by the slave boards, and the collected frequency is compared with a preset frequency; and a clock generation module of the mainboard is controlled to compensate and correct the frequency of the clock signal according to the comparison result. The clock frequency and thephase detected by each slave board are processed and analyzed through the control module of the main board, and the clock frequency and the phase of each single board are compensated and corrected according to the analysis result, so that the clock synchronization problem of the cross-board-level system is solved, the coordination work of multiple FPGAs is realized, the cross-board level homologous clock configuration and detection are realized, and a plurality of single boards can be flexibly stacked and used according to the number of required logic gates. The operations such as modulation,bias pulling, frequency modulation, frequency multiplication and the like are carried out on the clock signal to synthesize low-jitter and high-precision clock frequency, so that the stability of thesystem is improved.

Description

technical field [0001] The invention relates to the field of simulation testing, in particular to a cross-board homologous clock system. Background technique [0002] With the high integration of IC, more and more FPGA internal resources are used for verification. However, the resources of a single FPGA are limited and cannot meet the needs of IC simulation verification. Therefore, there is a strong demand for the coordination of multiple FPGAs. Due to the limitations of the board manufacturing process, a maximum of 4-6 FPGAs can be placed on a single board, which cannot meet the simulation requirements of tens of millions or even hundreds of millions of logic gate designs. However, a system built with multiple boards interconnected has high requirements for clock synchronization. Contents of the invention [0003] In order to solve the above-mentioned technical problem that the clock frequency cannot be synchronized in the prior art, the present invention proposes a cro...

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Problems solved by technology

[0003] In order to solve the technical problem that the clock frequency cannot be synchronized in the above-mentioned prior art, the present invention proposes a cross-board-level homologous clock system

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