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Method for automatically detecting system I2C address abnormity based on sequence traversal

An automatic detection and address technology, applied in error detection/correction, software testing/debugging, instruments, etc., can solve the problem of low efficiency of BMCI2C bus address anomaly detection, save manpower and material resources, improve detection efficiency, and speed up the research and development process. Effect

Active Publication Date: 2021-02-02
INSPUR SUZHOU INTELLIGENT TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The present invention provides a method for automatically detecting system I2C address abnormality based on layer order traversal to solve the current low efficiency of BMC I2C bus address abnormal detection

Method used

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  • Method for automatically detecting system I2C address abnormity based on sequence traversal
  • Method for automatically detecting system I2C address abnormity based on sequence traversal
  • Method for automatically detecting system I2C address abnormity based on sequence traversal

Examples

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Embodiment 1

[0058] as attached figure 1 As shown in the flow chart, the embodiment of the present invention provides a method for automatically detecting system I2C address abnormality based on layer sequence traversal, including:

[0059] Step S101: Design the detection process of the current BMC I2C bus address abnormality based on layer order traversal, and automatically scan all slave devices under the BMC I2C bus layer by layer according to the detection process, and determine the actual address of the slave devices under the current BMC I2C bus ;

[0060] Step S102: Obtain a preset address table, and determine whether the current I2C address is abnormal according to the comparison between the actual address of the slave device under the current BMC I2C bus and the preset address table;

[0061] Step S103: If there is no abnormality in the I2C address, then end the detection process;

[0062] Step S104: If there is an abnormality in the I2C address, give an early warning and output...

Embodiment 2

[0066] In one embodiment, the detection flow of the current BMC I2C bus address abnormality is designed based on layer sequence traversal, and all slave devices under the BMC I2C bus are automatically scanned layer by layer according to the detection flow to determine the current BMC I2C bus. The actual address of the slave device, including:

[0067] According to the abnormal detection process of designing the current BMC I2C bus address based on layer order traversal, all devices under the BMCI2C bus are automatically scanned layer by layer; wherein,

[0068] If the scanned device has an I2C address, the current device is the effective level;

[0069] If the scanned device does not have an I2C address, the current device is an invalid level;

[0070] According to the effective hierarchy, obtain the device addresses of all effective hierarchies, and determine the actual address of the slave device under the current BMC I2C bus;

[0071] The working principle of the above-me...

Embodiment 3

[0074] In one embodiment, as attached image 3 The hierarchical order traversal topology graph and attached Figure 5 As shown in the effective hierarchy topology diagram, if the scanned device has an I2C address, the current device is the effective hierarchy, including:

[0075] Based on the I2C devices below the effective level 3, it is determined that the effective level is not greater than 3 layers;

[0076] Because the I2C address of the I2C device below the effective level 3 cannot affect the first 3 layers, it can be determined that the effective level is not greater than 3 layers;

[0077] According to the effective level is not more than 3 layers, it is determined that it is only necessary to traverse the first 2 effective layers of the scan;

[0078] The working principle of the above-mentioned technical solution is: in practical applications, the I2C topology structure can have multiple layers, but the effective layer is only 3 layers at most—that is, the device a...

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Abstract

The invention provides a method for automatically detecting system I2C address abnormity based on sequence traversal. The method comprises the steps of designing a detection process of current BMC I2Cbus address abnormality based on layer sequence traversal, automatically scanning all slave devices under a BMC I2C bus layer by layer according to the detection process, determining actual addressesof the slave devices under the current BMC I2C bus, obtaining a preset address table, comparing the actual address of the slave device under the current BMC I2C bus with the preset address table, determining whether the current I2C address is abnormal or not,if the I2C address is not abnormal, marking the equipment as an effective level,and if the I2C address is abnormal, carrying out early warning and outputting an abnormal equipment address, and ending the detection process. The method has the beneficial effects that the method is used for effectively improving the detection efficiency of the address exception under the BMC I2C bus, saving manpower and material resources and accelerating the project research and development process, and is also suitable for the situation that other devices serve as hosts and downlink hitching is conducted on numerous I2C devices.

Description

technical field [0001] The invention relates to the technical field of detecting I2C address abnormalities, in particular to a method for automatically detecting system I2C address abnormalities based on layer sequence traversal. Background technique [0002] At present, the I2C (Inter-Integrated Circuit) bus is a two-wire serial bus developed by Philips, which is used to connect microcontrollers and their peripherals, so that master devices (such as processors, microcontrollers (MCU) or Application Specific Integrated Circuit (ASIC)) capable of communicating with other peripherals on the same two-wire bus. Of the two buses, one line is dedicated to data transfers, while the other is used for clock signals. Its benchmark speed is 100Kbit / S, the fast mode speed reaches 400Kbit / S, and the high-speed mode reaches 3.4Mbit / S. The 7-bit I2C bus can connect 127 I2C devices with different addresses. [0003] In today's server system design, the BMC is usually used as the host of ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/36G06F13/42
CPCG06F11/3684G06F11/3688G06F13/4282
Inventor 刘洋
Owner INSPUR SUZHOU INTELLIGENT TECH CO LTD
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