Chip verification method and device, electronic equipment and storage medium

A verification method and a verification device technology are applied in the fields of chip verification methods, devices, electronic equipment and storage media, and can solve problems such as inability to verify chips.

Pending Publication Date: 2020-11-17
HYGON INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Through multiple verifications, it is found that some scenarios are difficul

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  • Chip verification method and device, electronic equipment and storage medium
  • Chip verification method and device, electronic equipment and storage medium
  • Chip verification method and device, electronic equipment and storage medium

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Embodiment Construction

[0027] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

[0028] Universal Verification Methodology (Universal Verification Methodology, referred to as UVM) is a typical representative in chip verification. The most important multiplexing unit in the UVM architecture is the bus agent (Agent). The verifier generates transaction-level packets (transaction) by writing the sequence (Sequence) in the sequencer (Sequencer), and converts it into an interface stimulus through the driver (Driver). The signal acts on the bus interface, and the monitor (Monitor) collects the bus signal, converts it back into a transaction-level packet, and sends it to the scoreboard (scoreboard) for automatic comparison.

[0029] During chip verification, the UVM system is communicated with the device under test (DUT), and the UVM system sends the generated stimulus signal to the DUT...

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Abstract

The invention provides a chip verification method and device, electronic equipment and a storage medium. The method comprises the following steps: a verification platform sends a first verification request of a first preset channel to a chip, and forcibly pulls a signal of a second preset channel corresponding to a cyclic arbitration algorithm module, so that the cyclic arbitration algorithm module receives the request of a first preset channel and the request of a second preset channel; and the verification platform receives a first verification result sent by the chip, and the first verification result comprises a request and a response result corresponding to a target channel responded by the cyclic arbitration algorithm module according to the priority of the current channel signal soas to realize chip verification. According to the embodiment of the invention, the scene that the cyclic arbitration module receives the requests sent by the plurality of channels at the same time canbe covered, so that the chip can be verified more comprehensively.

Description

technical field [0001] The present application relates to the technical field of chip verification, and in particular, to a chip verification method, device, electronic equipment, and storage medium. Background technique [0002] With the continuous emergence of new technologies such as artificial intelligence AI, the requirements for human-computer interaction and intelligence are getting higher and higher, and the functions of chips will become more and more complex. From a design point of view, a system-on-chip SOC can define multiplexing technology based on kernel modules, and high-performance complex chips can be quickly developed by using off-the-shelf cores. From a functional point of view, an SOC can integrate the entire system on a chip, enabling The performance of the product is greatly improved, and the volume is significantly reduced. [0003] Since many functions are integrated on a chip, the chip needs to be verified after the chip is developed to ensure that ...

Claims

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Application Information

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IPC IPC(8): G06F11/26
CPCG06F11/26
Inventor 黄书茜
Owner HYGON INFORMATION TECH CO LTD
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