A Circuit for Rapid Gain Calibration of Phase-Locked Loop Digital-to-Time Converters

Abstract

The invention relates to a circuit for fast gain calibration of a digital time converter of a phase-locked loop, belonging to the technical field of analog integrated circuit design. The invention is composed of a digital time converter, an error measurement module, a gain calibration module, a digital controller, a frequency and phase detector, a charge pump, a voltage-controlled oscillator and a frequency divider. In the circuit of the present invention, the error measurer can provide a multi-bit error signal to the gain calibration module, and the time-to-digital converter is set to output a 4-bit binary error signal, which is used as the input of the integrator on the one hand, On the other hand, as the output of the error extractor, the error signal can not only indicate the lead / lag state of the two input signals of the time amplifier, but also indicate the specific lead / lag amount, which is equivalent to providing a more accurate signal for the LMS calibration module. More information, thereby accelerating the LMS calibration process of the analog phase-locked loop, thereby greatly improving the calibration speed of the analog phase-locked loop.

Description

technical field [0001] The invention relates to a circuit for fast gain calibration of a digital time converter of a phase-locked loop, belonging to the technical field of analog integrated circuit design. Background technique [0002] A phase-locked loop (hereinafter referred to as PLL) is the core circuit in various communication and clock chips. Spectral noise, jitter, spurious and other indicators of its output signal are very critical and will directly affect system performance. Fractional frequency-division phase-locked loop is an important type of phase-locked loop. It can achieve the effect that the output frequency is a non-integer multiple of the phase detection frequency by quickly switching the frequency division ratio of the feedback frequency divider. In this way, in a fixed channel The width allows the use of a high reference frequency, which reduces the in-band noise and improves the integral jitter performance of the phase-locked loop. However, if you want ...

AI Technical Summary

Problems solved by technology

Usually in actual implementation, only binary error information such as lead / lag is used to represent, so the error information provided to the calibration loop is too limited, and the calibration speed will be slow to the order of hundreds of microseconds or even milliseconds

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