Cache control method and system, storage medium, computer equipment and application

Abstract

The invention belongs to the technical field of data exchange and discloses a cache control method and system, a storage medium, computer equipment and an application. The method comprises the steps:enabling one Block RAM to be controlled into a plurality of three-channel synchronous FIFOs for use, writing data frames into corresponding on-chip FIFOs when the data frames enter a queue, and writing the data into an off-chip DDR after the on-chip FIFOs are fully written; dividing the DDR storage space into L area blocks with continuous addresses; when data dequeues, moving k continuous data frames to the on-chip FIFO from the DDR while the data is read from the corresponding on-chip FIFO. According to the invention, the processing speed and the traffic burst resistance of the packet processing unit are improved, the DDR bandwidth utilization rate is increased, and the time delay of DDR data reading is reduced. According to the invention, the processing speed of the switching unit is accelerated, a relatively high DDR bandwidth utilization rate is realized, and the influence of absolute time delay brought by a DDR device on the processing time of the switching unit is reduced.

Description

technical field [0001] The invention belongs to the technical field of data exchange, and in particular relates to a cache control method, system, storage medium, computer equipment and application. Background technique [0002] At present, the switching unit implemented with FPGA balances the problems of insufficient processing speed of the software switching unit and lack of flexibility of the dedicated ASIC chip, and has broad application prospects in the field of network switching. Use FPGA on-chip SRAM to store and forward data frames, which has the characteristics of high speed, low delay and easy control. Use external DDR to store data flow, which has the characteristics of large capacity and high bandwidth. [0003] In the prior art, FPGA directly plugs the DDR cache control method, which is used to solve the problem that the prior art cannot cope with traffic burst due to insufficient storage resources in the FPGA chip. Its technical scheme is: 1) DDR storage spac...

AI Technical Summary

Problems solved by technology

This method has the following deficiencies: 1. Although DDR has a large bandwidth, the arrival of Ethernet packets often has randomness. Different Ethernet packets are assigned different buffer addresses, and then the DDR read and write addresses generate multiple jumps. The physical bandwidth utilization rate of DDR is low, which limits the ability of the packet unit to resist traffic bursts

2. The reading and writing of DDR data needs to activate BANK first, then perform row addressing, then column addressing, and then write or read data. The characteristics of the device itself cause its read and write to have a fixed delay. This delay also causes packet unit data forwarding delay

[0004] Through the above analysis, the existing problems and defects of the existing technology are: the randomness of the arrival of Ethernet packets leads to low bandwidth utilization of directly using the external DDR for data storage and forwarding, which cannot meet high-speed traffic bursts, and the characteristics of the DDR device itself lead to data storage and forwarding. Packet processing has a large delay

[0005] The difficulty of solving the above problems and defects is as follows: if the problem of low bandwidth utilization and data packet processing delay caused by the characteristics of DDR devices in the process of data storage and forwarding by external DDR is to be solved, it is necessary to use the on-chip DDR at the same time. The buffer area performs data buffering, and the joint control of the on-chip buffer area and off-chip DDR puts forward higher requirements for queue buffer management to ensure that the data frames cannot be out of order, and at the same time, the system is pipelined to reduce the relative delay

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