Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

A detection method for wafer passivation layer defects

A detection method and passivation layer technology, which can be used in optical testing flaws/defects, measurement devices, semiconductor/solid-state device testing/measurement, etc., can solve the problems of missed inspection, structural defects, surface defects, etc. rate, wide application range, wide coverage effect

Active Publication Date: 2021-10-12
广芯微电子(广州)股份有限公司
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, the existing passivation layer detection technology has the following disadvantages: (1) defects include structural defects and surface defects
In view of cost considerations, some optical inspections only select some areas of the wafer for random inspection, so some tiny surface defects may be missed
There are also some tiny scratches due to their small size, if the resolution of the machine is not enough, they may be missed

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A detection method for wafer passivation layer defects
  • A detection method for wafer passivation layer defects
  • A detection method for wafer passivation layer defects

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0022] The improved wafer passivation layer defect detection method of the present invention can be used for detection of wafers of various sizes, but in this embodiment, the wafer to be tested is a 12-inch product wafer whose top layer metal is copper.

[0023] The steps of the detection method for the defects of the wafer passivation layer in this embodiment are:

[0024] (1) Provide a 12-inch wafer to be tested that has been inserted into a specific interdigitated structure detection circuit in the dicing groove during the import stage of the design file, and perform a WAT ​​test on these detection circuits to obtain their capacitance and resistance values;

[0025] Such as figure 1 As shown, in order to monitor the stability of the on-line process, a specific test structure will be inserted on the scribe groove between the chips in the wafer. The density of the inserted electrical monitoring structure and the structure of the detection circuit are determined by the requir...

Embodiment 2

[0034] The difference between Embodiment 2 and Embodiment 1 is that the wafer to be tested is a 12-inch product wafer with a different chip circuit structure. The defect rate of the wafer passivation layer of the 12-inch wafer described in this embodiment after being detected by AEI is 0.51%, and the defect rate of the wafer passivation layer obtained through the detection steps of this embodiment is 0.56%, and the detection result is consistent with that of Example 1 Similarly, although the defect rate of the passivation layer of the product wafer in this embodiment is higher and the pass rate is slightly lower, the defect discovery rate of the detection method used in the present invention is still higher than that of the traditional optical AEI detection method.

Embodiment 3

[0036]The difference between embodiment 3 and embodiment 1 is that the wafer to be tested is a 12-inch test control chip wafer whose top metal is copper and the chip circuit structure is different. The defect rate of the wafer passivation layer of the 12-inch wafer described in this embodiment is 3.89% after the AEI detection, and the defect rate of the wafer passivation layer obtained through the detection steps of this embodiment is 4.21%, showing that the passivation layer provided by the present invention has a defect rate of 4.21%. The chemical layer defect detection method can be applied to normal product wafers or control wafers with many defects for detection and testing, and the accuracy and precision are higher than the AEI detection method.

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a method for detecting defects in a wafer passivation layer, comprising the following steps: (1) in the design file import stage, inserting a detection circuit structure in the wafer scribing groove area; in the wafer WAT test stage, testing The previous value of capacitance and the previous value of resistance of the detection circuit structure in the wafer; (2) after the wafer described in step (1) is pressure cooked, the wafer surface is cleaned; (3) after step (2) is cleaned Carry out the WAT test on the same scribe groove area of ​​the wafer again, and compare the obtained capacitance and resistance values ​​with the previous values ​​obtained in step (1), so as to determine whether there is a defect in the passivation layer of the wafer. The method improves the low detection rate of passivation layer defects caused by the limitations of the current instrument resolution and detection range, and reduces the missed detection rate in the sampling inspection process. At the same time, the detection method can be applied to random inspection on wafers of various sizes and regular routine inspection in fabs.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a method for detecting defects in a passivation layer of a wafer. Background technique [0002] In the process of producing wafers in the fab, for non-bumping (bumping) packaged products, a passivation layer composed of silicon dioxide will be covered at the end. The passivation layer can effectively isolate moisture and physically protect the chip. If the passivation layer is defective, it will not provide effective protection and provide a potential pathway for moisture to enter the chip interior. At present, the color of the passivation layer is mainly observed by optical methods such as manual visual inspection or machine AEI (after each inspection), whether there are abnormal scratches, stains, or foreign particles. [0003] However, the existing passivation layer detection technology has the following disadvantages: (1) Defects include structural defects and surface defects....

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66G01N21/95
CPCG01N21/9505H01L22/12H01L22/14
Inventor 王锐杨侃诚王亚波莫军李建军
Owner 广芯微电子(广州)股份有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products