FPGA hard start method and device supporting multiple mirror images

Abstract

The embodiment of the invention provides a field programmable gate array chip and a configuration method thereof. The field programmable gate array chip at least comprises a starting module. The starting module is used for realizing starting logic of the field programmable gate array chip by hardware in advance, and the method comprises the following steps: after the field programmable gate arraychip is electrified, executing the starting logic of the field programmable gate array chip through the starting module, and starting the field programmable gate array chip; and the started field-programmable gate array chip reading different application configuration data from an external memory, and configuring the field programmable gate array chip. By means of the field programmable gate arraychip and the configuration method thereof, the starting and configuration time of the field programmable gate array chip can be accelerated, meanwhile, the occupation of field programmable gate arraychip starting on field programmable gate array user logic resources is reduced, and the space of an external memory for storing configuration information is saved.

Description

technical field [0001] The present invention relates to the technical field of Field Programmable Gate Array (FPGA), in particular to a hard-core Boot system supporting multiple images in the FPGA. Background technique [0002] FPGA, Field Programmable Gate Array (Field Programmable Gate Array) is a logic device composed of many logic units. After manufacturing, the FPGA can be reprogrammed according to the required application or functional requirements. As a semi-custom circuit, it has rich hardware resources, powerful parallel processing capability and flexible reconfigurable capability, and has a wide range of applications in many fields such as data processing, communication, and network. [0003] During the startup process of the FPGA, many FPGA applications save multiple mirror images in the external memory (such as Flash). When the FPGA is powered on, it is necessary to read the boot (Boot) function code stream from the default address of the Flash first, and config...

AI Technical Summary

Problems solved by technology

For some applications that require high system startup time, there may be problems that cannot meet the configuration time requirements

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