Successive approximation type analog-to-digital converter with capacitance mismatch correction function

Abstract

The invention discloses a successive approximation type analog-to-digital converter with a capacitor mismatch correction function. The circuit is provided with a P-end DAC (102), an N-end DAC (104), acomparator (106), an SAR logic circuit (108), a correction logic circuit (110) and a correction control circuit (112). The output end of the P-end DAC (102) and the output end of the N-end DAC (104)are respectively connected with two input ends of the comparator (106). Wherein the output of the comparator (106) is connected with the SAR logic circuit (108); the SAR logic circuit (108) is in control connection with the P-end DAC (102), the N-end DAC (104) and the correction logic circuit (110); and the correction control circuit (112) is in control connection with the SAR logic circuit (108)and the correction logic circuit (110).

Description

technical field [0001] The invention relates to the field of analog integrated circuit technology and the like, specifically, a successive approximation analog-to-digital converter with capacitance mismatch correction function. Background technique [0002] SAR_ADC (Successive Approximation Analog-to-Digital Converter) is a common architecture of ADC (Analog-to-Digital Converter). The charge redistribution SAR_ADC using capacitor array has become the mainstream structure of SAR_ADC due to good capacitor matching and low static power consumption. Usually, an N-bit SAR_ADC contains an N-bit binary capacitor array, namely 1C, 2C, 4C, ..., 2N-1C, where C is the unit capacitance, 2N-1C corresponds to the MSB (highest bit), and 1C corresponds to the LSB (lowest bits). [0003] For high-resolution SAR_ADC, such as N=14 or 16, the binary capacitor array will occupy a large chip area, and the maximum capacitance and minimum capacitance are very different, making it difficult to ach...

AI Technical Summary

Problems solved by technology

Using a non-binary capacitor array can eliminate the dynamic error caused by incomplete DAC establishment or reference voltage jitter during the quantization process, but the value of each capacitor is no longer equal to the sum of all its low-level capacitors, making the above-mentioned foreground self-calibration no longer applicable

In addition, the use of auxiliary DAC increases the circuit area and power consumption

[0012] For background self-calibration, it involves the convergence of the algorithm. Once the system parameters are improperly selected, the algorithm may not converge

In addition, for deep submicron CMOS (complementary metal oxide semiconductor) processes, such as 0.35 μm CMOS or 0.18 μm CMOS processes, the hardware overhead of digital circuits is still very large compared to nanoscale CMOS processes

At present, some mainstream high-precision and low-speed SAR_ADC are still designed and manufactured on deep submicron process lines, so it is not suitable for background self-calibration

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