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A kind of 3D NAND memory structure and preparation method thereof

A 3DNAND, storage structure technology, applied in semiconductor devices, electrical components, circuits, etc., can solve problems such as storage area loss, and achieve the effects of increasing storage area, improving stress resistance, and reducing parasitic capacitance

Active Publication Date: 2021-08-13
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a 3D NAND storage structure and its preparation method, which is used to solve the problems caused by the large feature size when the traditional method forms a gate gap on the front side of the wafer. The problem of certain storage area loss

Method used

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  • A kind of 3D NAND memory structure and preparation method thereof
  • A kind of 3D NAND memory structure and preparation method thereof
  • A kind of 3D NAND memory structure and preparation method thereof

Examples

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Embodiment 1

[0124] Such as figure 1 As shown, the present embodiment provides a method for preparing a 3D NAND storage structure, the preparation method comprising:

[0125]S1: Provide a semiconductor intermediate structure 10, the semiconductor intermediate structure 10 includes: a semiconductor substrate 101, a stacked structure 116 formed on the semiconductor substrate 101 and a front gate formed in the stacked structure 116 A gap 112; wherein, the front gate gap 112 runs through the stacked structure 116 and extends to the semiconductor substrate 101;

[0126] S2: forming an initial common source line 13 on the inner wall of the front gate gap 112 to fill the front gate gap 112;

[0127] S3: forming a back gate gap 16 on a surface of the semiconductor substrate 101 away from the opening of the front gate gap 112, wherein the back gate gap 16 exposes the bottom of the initial common source line 13;

[0128] S4: forming a common source line 19 on the inner wall of the back gate gap 16...

Embodiment 2

[0194] Such as Figure 23 As shown, the present embodiment provides a 3D NAND storage structure, and the storage structure includes:

[0195] The semiconductor intermediate structure 10, the semiconductor intermediate structure 10 includes: a semiconductor substrate 101, a stacked structure 116 formed on the semiconductor substrate 101, and a front gate gap 112 formed in the stacked structure 116, wherein , the front gate gap 112 runs through the stacked structure 116 and extends to the semiconductor substrate 101;

[0196] an initial common source line 13 formed in the front gate gap 112;

[0197] a back gate gap 16 formed in the semiconductor substrate 101, wherein the back gate gap 16 exposes the bottom of the initial common source line 13;

[0198] The common source line 19 is formed in the back gate gap 16 .

[0199] Since the 3D NAND storage structure described in this example forms a back gate gap 16 on the back side of the semiconductor substrate 101 and leads a com...

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Abstract

The present invention provides a 3D NAND storage structure and a preparation method thereof. The preparation method includes: providing a semiconductor intermediate structure, and the semiconductor intermediate structure includes: a semiconductor substrate, a stacked structure formed on the semiconductor substrate, and a A front gate gap in the stacked structure; wherein, the front gate gap penetrates the stacked structure and extends to the semiconductor substrate; an initial common source line is formed on the inner wall of the front gate gap , to fill the front gate gap; form a back gate gap on a surface of the semiconductor substrate away from the opening of the front gate gap, wherein the back gate gap exposes the initial common source line Bottom; forming a common source line on the inner wall of the back gate gap to fill the back gate gap. The present invention solves the existing problem of loss of storage area due to larger feature size when forming front gate gaps on the front side of the wafer.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design and manufacture, and in particular relates to a 3D NAND storage structure and a preparation method thereof. Background technique [0002] In recent years, the development of flash memory (Flash Memory) has been particularly rapid. The main feature of flash memory is that it can keep stored information for a long time without power on, and it has high integration, fast access speed, easy erasing and resetting. It has the advantages of writing and so on, so it has been widely used in many fields such as microcomputer and automatic control. In order to further increase the bit density (Bit Density) of the flash memory while reducing the bit cost (Bit Cost), three-dimensional flash memory (3D NAND) technology has been developed rapidly. [0003] As the number of 3D NAND memory layers increases, the gate gap (GLS:Gate Line Slit) process challenge is getting bigger and bigger; the tra...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/1157H01L27/11582
CPCH10B43/35H10B43/27
Inventor 孙中旺吴林春张坤王迪周文犀
Owner YANGTZE MEMORY TECH CO LTD
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