Array substrate, preparation method thereof and display panel

Abstract

The invention relates to the technical field of the display and discloses an array substrate and a preparation method thereof, and a display panel. The preparation method comprises the following steps: sequentially forming a shielding layer, a buffer layer, an active layer, a gate insulating layer and a first metal layer on a substrate, and completely reserving parts corresponding to a gate wiringarea of the first metal layer through a composition process; forming a second metal layer on the first metal layer, forming a photoresist layer on the second metal layer, and forming a gate pattern,a gate wiring pattern and a photoresist pattern such that a relatively large first line width deviation is formed between photoresist covering the gate pattern and the gate pattern and a second line width deviation is formed between the photoresist covering the gate wiring pattern and the gate wiring pattern; forming a gate insulating layer pattern; and performing a conductor process on a to-be-conducted region. According to the preparation method of the array substrate, by optimizing the preparation scheme, the TFT characteristic and the metal wiring conductivity requirement can be met at thesame time, the breaking risk of a metal wire can be reduced, and the display quality of a product is improved.

Description

technical field [0001] The invention relates to the field of display technology, in particular to an array substrate, a preparation method thereof, and a display panel. Background technique [0002] The top-gate thin film transistor (Thin Film Transistor, referred to as TFT) has the characteristics of a short channel, so its on-state current Ion can be effectively increased, so that the display effect can be significantly improved and power consumption can be effectively reduced. Moreover, the overlap area between the gate and the source and drain of the top-gate TFT is small, so the parasitic capacitance generated is small, so the possibility of defects such as GDS (Gate DrainShort, that is, short circuit between the gate and the drain) is also reduced. Since the top-gate TFT has the above-mentioned remarkable advantages, it has attracted more and more attention. [0003] In the top-gate active matrix organic light emitting diode (Active-matrix organic light emitting diode...

AI Technical Summary

Problems solved by technology

This is in contradiction with the above-mentioned active layer conductorization process that requires a large line width deviation formed after the gate 06 is etched.

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