Array substrate, preparation method thereof and display panel

A technology of array substrates and substrate substrates, which is applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc., can solve problems such as large line width deviation, prevent line width from being too narrow, ensure stability, and enhance electrical conductivity effect of ability

Active Publication Date: 2020-06-19
HEFEI XINSHENG OPTOELECTRONICS TECH CO LTD +1
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  • Application Information

AI Technical Summary

Problems solved by technology

This is in contradiction with the above-mentioned active layer conductorization process that requires a large line width deviation formed after the gate 06 is etched.

Method used

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  • Array substrate, preparation method thereof and display panel
  • Array substrate, preparation method thereof and display panel
  • Array substrate, preparation method thereof and display panel

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Embodiment Construction

[0035] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0036] Please refer to Figure 3a-Figure 3e , the present invention provides a method for preparing an array substrate, comprising:

[0037] forming a shielding layer 2 on the base substrate 1;

[0038] Forming a buffer layer 3 on the shielding layer 2;

[0039] Form the active layer 4 on the buffer layer 3, and form the pattern of the active layer 4 through a patterning process. The pattern of the active layer 4 includes a channel portion 42 and regions 41 ...

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Abstract

The invention relates to the technical field of the display and discloses an array substrate and a preparation method thereof, and a display panel. The preparation method comprises the following steps: sequentially forming a shielding layer, a buffer layer, an active layer, a gate insulating layer and a first metal layer on a substrate, and completely reserving parts corresponding to a gate wiringarea of the first metal layer through a composition process; forming a second metal layer on the first metal layer, forming a photoresist layer on the second metal layer, and forming a gate pattern,a gate wiring pattern and a photoresist pattern such that a relatively large first line width deviation is formed between photoresist covering the gate pattern and the gate pattern and a second line width deviation is formed between the photoresist covering the gate wiring pattern and the gate wiring pattern; forming a gate insulating layer pattern; and performing a conductor process on a to-be-conducted region. According to the preparation method of the array substrate, by optimizing the preparation scheme, the TFT characteristic and the metal wiring conductivity requirement can be met at thesame time, the breaking risk of a metal wire can be reduced, and the display quality of a product is improved.

Description

technical field [0001] The invention relates to the field of display technology, in particular to an array substrate, a preparation method thereof, and a display panel. Background technique [0002] The top-gate thin film transistor (Thin Film Transistor, referred to as TFT) has the characteristics of a short channel, so its on-state current Ion can be effectively increased, so that the display effect can be significantly improved and power consumption can be effectively reduced. Moreover, the overlap area between the gate and the source and drain of the top-gate TFT is small, so the parasitic capacitance generated is small, so the possibility of defects such as GDS (Gate DrainShort, that is, short circuit between the gate and the drain) is also reduced. Since the top-gate TFT has the above-mentioned remarkable advantages, it has attracted more and more attention. [0003] In the top-gate active matrix organic light emitting diode (Active-matrix organic light emitting diode...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/12H01L21/77
CPCH01L27/1288H01L27/1244
Inventor 刘宁宋威苏同上刘烺张大成王红丽
Owner HEFEI XINSHENG OPTOELECTRONICS TECH CO LTD
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