Variable-parameter digital image multi-scale convolution processor and its realization method

Abstract

The invention relates to a digital image multi-scale convolution processor with variable parameters and its implementation method. The processor includes a communication unit, a main control unit, a digital image data buffer unit, a multi-scale convolution operation unit and a convolution parameter storage unit. , the implementation method includes that the communication unit receives instruction information and parameter information from a host computer or a microprocessor, analyzes the instruction information and parameter information, and sends them to the main control unit; the main control unit updates the convolution parameters in the convolution parameter storage unit, Then enable the digital image data cache unit, receive digital image data and generate a data flow window; read the convolution parameters and pass them to the corresponding convolution operation subunit; enable the convolution operation subunit in the multi-scale convolution operation unit , perform a convolution operation, and output the digital image data after the convolution operation. The invention can modify the convolution parameters on the spot without reprogramming, and can realize the convolution processing of the same digital image in multiple scales in parallel at the same time, and has high real-time performance.

Description

technical field [0001] The invention relates to the technical field of digital image processing, in particular to a digital image multi-scale convolution processor with variable parameters and an implementation method thereof. Background technique [0002] In the practical application of digital image processing, convolution processing is a very important digital image preprocessing method. According to the different convolution parameters, it can be used to complete the underlying image processing operations such as digital image denoising, enhancement, and edge extraction. However, a large number of multiplication, addition and division operations are involved in the convolution processing of digital images. How to ensure the real-time performance of convolution processing is a very critical issue, which will directly affect the subsequent links of digital image processing. [0003] There are three main ways to implement the existing digital image convolution processing: ...

AI Technical Summary

Problems solved by technology

[0004] The first implementation is based on a high-performance microprocessor, mainly represented by a high-performance digital signal processor (DSP). This processing method first stores the received digital image in a data array, and waits After receiving a complete digital image data, the convolution processing of the digital image is completed by software. This implementation method has high software overhead and large delay, and it is difficult to adapt to the occasions that require high real-time digital image processing.

[0005] The second implementation is to use a dedicated digital image convolution processor. This processing method usually has a small delay and can adapt to high real-time digital image processing occasions. However, this processing method usually has fixed convolution parameters, and its Less flexible and scalable

[0006] The third processing method is based on field programmable gate array (FPGA) or complex programmable logic device (CPLD). Large and small digital image data can be processed correspondingly, and the delay is relatively small, which can be adapted to some real-time digital image processing occasions. However, this implementation method needs to modify the convolution parameters to adapt to different application scenarios. When dealing with convolution tasks in different scales of the same digital image, it is necessary to modify the logic program in the Field Programmable Gate Array (FPGA) or Complex Programmable Logic Device (CPLD), which is time-consuming and laborious.

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