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Configuration object control method and device, storage medium and verification platform

A technology for configuring objects and verifying platforms, which is applied in special data processing applications, instruments, electrical digital data processing, etc., and can solve problems such as redundant codes

Active Publication Date: 2020-06-09
NANJING SEMIDRIVE TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Embodiments of the present application provide a configuration object control method, device, storage medium, and verification platform, which are used to solve the problem of setting context identifiers for configuration objects and generating a large number of redundant codes

Method used

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  • Configuration object control method and device, storage medium and verification platform
  • Configuration object control method and device, storage medium and verification platform
  • Configuration object control method and device, storage medium and verification platform

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Embodiment Construction

[0029] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the following will further describe the embodiments of the present application in detail in conjunction with the accompanying drawings.

[0030] Currently, there are multiple verification methodologies applied to chip verification, and different verification methodologies correspond to different standard basic development libraries and verification platform architectures. Among them, UVM (Universal Verification Methodology, Universal Verification Methodology) is currently the most widely used verification methodology. In this embodiment, a verification platform based on UVM is taken as an example for description.

[0031] The construction of the verification platform includes the development of verification components (VIP) such as low-level signal drivers (drivers), signal monitors (monitors), and high-level transaction comparators (checkers); the int...

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PUM

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Abstract

The embodiment of the invention discloses a configuration object control method and device, a storage medium and a verification platform, and belongs to the technical field of testing. The method is used in a verification platform, the verification platform comprises a verification assembly and a test sequence, the verification assembly is used for testing a tested object according to the test sequence, and the method comprises the steps of acquiring a test case to control the verification assembly or the test sequence; analyzing the test case; obtaining control information of a first configuration object in the verification component or the test sequence, wherein the control information comprises a full path name of a first node corresponding to the first configuration object in the treenetwork, a root node in the tree network corresponds to a configuration object corresponding to the verification platform, and the rest nodes correspond to configuration objects corresponding to the verification component or configuration objects corresponding to the test sequence; acquiring control information according to the full path name by utilizing the first configuration object; and controlling the first configuration object to execute the operation indicated by the control information. The embodiment of the invention can achieve the effect of simplifying the code.

Description

technical field [0001] The embodiments of the present application relate to the technical field of testing, and in particular to a control method, device, storage medium and verification platform for configuring objects. Background technique [0002] The process of verifying a chip can roughly include three parts: building a verification platform, writing a test sequence, and writing a test case. Among them, building a verification platform includes developing verification components, integrating verification components and chips under test, etc.; writing test sequences includes developing incentive sequences or control procedures for chip application scenarios; writing test cases includes testing configurable verification components and The test sequence is controlled to obtain a signal-level drive sequence specific to the test case, so as to drive and test the chip under test. [0003] With the continuous expansion of the chip scale, the application scenarios of the verif...

Claims

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Application Information

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IPC IPC(8): G06F30/398
CPCY02P90/02
Inventor 沈晓彭俊
Owner NANJING SEMIDRIVE TECH CO LTD
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