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Multiplier, data processing method, chip and electronic equipment

A multiplier and data technology, applied in the computer field, can solve the problems of signal inversion and multiplier power consumption, and achieve the effect of reducing power consumption and ensuring the accuracy of operation

Inactive Publication Date: 2020-06-09
SHANGHAI CAMBRICON INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004]However, in the traditional technology, the inversion and addition operation of the negative coded signal will cause the signal to be reversed, resulting in more power consumption of the multiplier

Method used

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  • Multiplier, data processing method, chip and electronic equipment
  • Multiplier, data processing method, chip and electronic equipment
  • Multiplier, data processing method, chip and electronic equipment

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Embodiment Construction

[0061] In order to make the purpose, technical solutions and advantages of the present application more clearly understood, the present application will be described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application.

[0062] The multiplier provided by this application can be applied to AI chips, Field-Programmable Gate Array (FPGA) chips, or other hardware circuit devices to perform multiplication processing. The specific structure diagram is as follows: figure 1 and 2 shown.

[0063] figure 1 A specific structural schematic diagram of a multiplier provided for an embodiment, such as figure 1 As shown, the multiplier includes: a Booth coding circuit 11, a modified partial product acquisition circuit 12, a Wallace tree group circuit 13 and an accumulation circuit 14, the output of...

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Abstract

The invention provides a multiplier, a data processing method, a chip and electronic equipment. The multiplier comprises: a Booth encoding circuit, a corrected partial product acquisition circuit, a Wallace tree group circuit and an accumulation circuit. The output end of the Booth encoding circuit is connected with the input end of the correction partial product acquisition circuit, the output end of the correction partial product acquisition circuit is connected with the input end of the Wallace tree group circuit, and the output end of the Wallace tree group circuit is connected with the input end of the accumulation circuit. According to the multiplier, on the premise that the operation accuracy of the multiplier can be completely guaranteed, when an original partial product is obtained due to a negative coded signal, carry forward transmission is possibly generated due to the fact that negation plus one operation needs to be conducted, and consequently multi-bit data signals are overturned is eliminated, and the power consumption of the multiplier is effectively reduced.

Description

technical field [0001] The present invention relates to the field of computer technology, in particular to a multiplier, a data processing method, a chip and an electronic device. Background technique [0002] With the continuous development of digital electronic technology, the rapid development of various artificial intelligence (Artificial Intelligence, AI) chips has higher and higher requirements for high-performance digital multipliers. Neural network algorithm, as one of the algorithms widely used in smart chips, multiplication operation by multiplier is a common operation in neural network algorithm. [0003] At present, most multipliers use the Booth algorithm to obtain partial products, compress the partial products through Wallace trees, and use a set of full adders to accumulate the compressed results to obtain the operation results. Among them, in Booth's algorithm, the negative coded signal needs to be inverted and added to obtain the partial product. [0004]...

Claims

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Application Information

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IPC IPC(8): G06F7/523
CPCG06F7/523
Inventor 不公告发明人
Owner SHANGHAI CAMBRICON INFORMATION TECH CO LTD
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