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FPGA parallel implementation method of PFA

An implementation method and azimuth technology, which is applied in the reflection/re-radiation of radio waves, the use of re-radiation, measurement devices, etc., can solve the problem that DSP is difficult to meet the real-time performance, etc., to improve real-time imaging performance, clear data flow, and improve real-time effects

Pending Publication Date: 2020-06-09
CHINA ELECTRONICS TECH GRP CORP NO 14 RES INST
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Problems solved by technology

However, as the requirements of SAR imaging system in terms of performance, power consumption and reliability continue to increase, DSP has become more and more difficult to meet the real-time requirements.

Method used

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  • FPGA parallel implementation method of PFA
  • FPGA parallel implementation method of PFA
  • FPGA parallel implementation method of PFA

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Embodiment Construction

[0014] The technical solution of the present invention will be specifically described below in conjunction with the accompanying drawings.

[0015] An FPGA parallel implementation of a PFA, such as figure 1 As shown, the AD chip writes the intermediate frequency sampling data of the radar baseband echo into the dual-channel DDR1 and DDR2 temporary storage through the high-speed serial bus, calculates the radar parameters required for the scale transformation in the range processing and azimuth processing, and stores them in the In the two groups of RAMs, PCS-based PFA processing is performed in parallel at the same time, including a series of FFT and complex multiplication operations to complete data modulus calculations and image quantization.

[0016] The parameter calculation is completed by several calculation modules, such as figure 2 As shown, it includes fixed-point to floating-point module, angle parameter calculation module, distance parameter calculation module, pa...

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Abstract

The invention discloses an FPGA parallel implementation method applied to a polar coordinate format algorithm in an airborne SAR real-time processing system and solves defects that an existing signalprocessing platform is insufficient in processing capacity and low in imaging precision under the requirements of extremely low power consumption, light weight limitation and miniaturization. A PFA high-precision imaging algorithm is adopted, engineering improvement of the algorithm is carried out on the basis of the Chirp Scaling principle (PCS), distance direction interpolation can be equivalently realized through two FFT operations, calculation is greatly reduced, acceleration processing of a polar coordinate format algorithm is achieved efficiently in parallel in an FPGA chip, and algorithm execution efficiency and the processing speed of a real-time imaging system are improved. The method is applied to an airborne SAR real-time processing system, has the capacity of conducting continuous and stable high-resolution imaging on the ground, has high application value and is worthy of popularization.

Description

technical field [0001] The invention belongs to the technical field of radar real-time imaging, and in particular relates to an FPGA parallel implementation method of PFA. Background technique [0002] Synthetic aperture radar can acquire high-resolution ground images all-weather and all-weather, and has been widely used in military and civilian fields, and has become an important development direction in the field of modern radar technology. As an important working method of imaging radar, spotlight SAR can obtain higher-resolution images by adjusting the beam pointing to irradiate a fixed area for a long time, breaking through the limitation of the maximum resolution of half the antenna azimuth aperture length in strip SAR mode. At present, the Polar Format Algorithm (PFA) is the most widely used in real-time spotlight SAR imaging. PFA uses the polar coordinate format to store data, which not only effectively solves the problem of moving beyond the resolution unit far away...

Claims

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Application Information

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IPC IPC(8): G01S13/90G01S7/292
CPCG01S13/9011G01S7/292
Inventor 赵敬亮崔爱欣杜婉婉朱岱寅郑昱庄龙沈石坚聂鑫
Owner CHINA ELECTRONICS TECH GRP CORP NO 14 RES INST
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