FPGA-based neural network calculator generation method and device

Abstract

The invention discloses an FPGA-based neural network calculator generation method and device. The method comprises the steps of determining a dependency relationship of each network layer in a neuralnetwork; grouping the network layers, wherein the dependency relationship of the network layers in each group are the same; determining the size of an array block required by each group; and deployingand deploying the FPGA according to the dependency relationship of the network layer in each group and the size of the array block required by each group so as to obtain the calculator of the neuralnetwork. According to the method, network layers which do not depend on each other (i.e., have the same dependency relationship) are divided into one group by analyzing the dependency relationship ofthe neural network, so that parallel computing can be realized in the array blocks allocated to the network layers, the critical path length is effectively shortened, and the computing efficiency is improved. In addition, the positions of the array blocks required by each group are arranged on the FPGA according to the dependency relationship, so that data exchange between arrays can be reduced, and the calculation efficiency is further improved.

Description

technical field [0001] The invention relates to the technical field of pulsation array applications, in particular to an FPGA-based neural network calculator generation method and device. Background technique [0002] A neural network is a commonly used computing structure in deep learning applications, and the implementation of this computing structure is implemented on an FPGA using a systolic array computing architecture. It is a challenging design problem to enable the systolic array architecture on the FPGA to quickly and accurately perform large-scale neural network calculations, which requires consideration of both computing and communication factors. [0003] In the prior art, in the multi-block arrays included in the computing architecture designed for the neural network, there is usually a problem that the array needs to be calculated serially, resulting in a long critical path length, and the computing efficiency of the computing architecture is low, thereby reduc...

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Problems solved by technology

[0003] In the prior art, in the multi-block arrays included in the computing architecture designed for the neural network, there is usually a problem that the array needs to be calculated serially, resulting in a long critical path length, and the computing efficiency of the computing architecture is low, thereby reducing the pulsation of the array. Architecture Efficiency

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