A Cell Matrix Merging Method in Physical Verification of Flat Panel Display Layout

Abstract

A cell matrix merging method in physical verification of flat panel display layout, comprising the following steps: 1) performing topological sorting of cells, sorting all cells from top to bottom according to a hierarchical reference relationship, and forming a linked list; 2) specifying a current cell, and performing element sorting Recognition of the matrix; 3) The calculation unit refers to the overlapping area, and divides the current unit into multiple blocks according to the overlapping area; 4) In each overlapping area block, merge the overlapping matrices in sequence to form a new unit , form a matrix of new units; 5) Insert a new unit linked list after the current unit, maintaining the topological order of the entire linked list. The unit matrix merging method in the physical verification of the layout of the flat panel display of the present invention reduces the overlapping area between the unit references to the greatest extent, avoids the occurrence of the worst situation of the layout layout, significantly improves the execution efficiency, and significantly optimizes the result level. And the follow-up operations are very positive.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit design, in particular to a physical layout verification tool for flat panel display circuits in semiconductor integrated circuit design, and in particular to a cell matrix merging method in physical verification of flat panel display layout. Background technique [0002] Flat Panel Display (FPD) devices, including mobile phone screens, computer monitors, TV screens, etc., whose main area is a display pixel array (Pixel Array) in the center of the device superimposed on a touch matrix (TouchArray), which consists of a large number of repetitive circuits The cells are arranged in rows and columns, and the control circuit is usually around the main area. [0003] To ensure the successful manufacture of flat panel display devices, the flat panel display circuits are also physically verified. Similar to the physical verification of the integrated circuit layout, the physical v...

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Problems solved by technology

Then, the execution efficiency of verification checks and the hierarchy of verification results are greatly affected by the original layout of the layout

In the best case, the reference of the pixel unit is not covered at all, the verification operation is performed inside the unit, and the inspection result is also generated inside the unit, and only one copy of the result is generated for the whole layout; in the worst case, if the reference of the pixel unit is replaced by other The unit reference is completely covered, and the verification operation of the pixel unit can only be performed in its parent unit (usually the top-level unit). As many pixels as there are, how many operations must be performed and how many results are generated, and the inspection efficiency is extremely low

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