Bus arrays for reduced storage overhead

Abstract

The present invention provides a collective element (CE, collective element) array for reducing storage overhead, including a plurality of CEs, each CE contains a local memory, each CE can receive data from outside the array or adjacent CEs, each CE can temporarily store the received data in the internal cache or output it out of the array. The invention broadcasts the data in one memory to multiple output ports through the data transfer inside the CE array, thereby effectively removing the data redundancy between different memories. And while reducing memory capacity requirements, additional power consumption caused by reading the same data from different memories is reduced.

Description

technical field [0001] The invention relates to the technical field of computer architecture, in particular to a collective element array for reducing storage overhead. Background technique [0002] In recent years, deep learning has gradually achieved more and more remarkable results in fields such as image recognition and speech processing. However, as the depth of the network continues to increase, the computing power and memory access bandwidth required in the training and inference process of the deep neural network are gradually difficult to be met by traditional computing platforms. Therefore, various domain-specific architectures (domain specified architectures) applied to neural networks have been proposed by the industry and academia to meet this requirement. Among them, the systolic array architecture has attracted great attention from the industry and academia due to its characteristics of high concurrency and low bandwidth requirements. Based on this, the inve...

AI Technical Summary

Problems solved by technology

However, when the number of computing units and memories is large, the bandwidth requirement is large, and the memory access behavior is relatively regular, the bus-based connection method has a certain waste in terms of area, cycle, and timing.

In addition, due to various reasons, different memories often contain multiple copies of the same data segment, resulting in a waste of capacity

At the same time, during the operation of the chip, because the same data needs to be written into multiple memories and read repeatedly from multiple memories, this causes additional power consumption overhead

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