A sparse neural network accelerator and its implementation method

Abstract

The present invention provides a sparse neural network accelerator and its implementation method. The accelerator mainly includes a PE array, an output memory, and a scheduler module. The PE array is divided into multiple PE groups, and each PE group and the corresponding output memory form an associated group. The number of PEs in the association group is equal to the number of output memories; each PE unit in the association group can access any output memory in the association group; PE units in any association group are calculated according to the input activation value and weight value Multiple output results are obtained and written into corresponding multiple output memories according to preset rules; the scheduler module schedules the sequence of output activation values ​​to reduce the probability of hash collisions. The invention divides the original PE array into multiple PE groups, and forms an associated group architecture with the corresponding output memory, which greatly reduces the area of ​​the output memory and reduces power consumption; the scheduler module reduces the probability of hash conflicts and greatly improves the Computational performance of the entire system.

Description

technical field [0001] The invention belongs to the technical field of neural network accelerators, in particular to a sparse neural network accelerator and an implementation method thereof. Background technique [0002] Convolutional Neural Networks (CNNs) have shown promising performance in many domains. However, CNN networks have considerable computational and storage complexity, so application-specific integrated circuit (ASIC) accelerators need to be designed to speed up the computation of CNNs. At the same time, existing high-efficiency CNNs have high sparsity (the proportion of 0 in network parameters and intermediate results is high), so existing accelerators adopt different hardware designs to accelerate the calculation of sparse neural networks. [0003] Existing ASIC designs have taken different approaches to handle sparse CNNs. The first method is the power gating method, which improves energy efficiency by turning off the corresponding computing unit (PE) when...

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Problems solved by technology

[0006] In order to overcome the above-mentioned problem of high power consumption of the existing output memory or at least partially solve the above-mentioned problem, an embodiment of the present invention provides a sparse neural network accelerator and its implementation method

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