Semiconductor structure and formation method thereof

Abstract

The invention discloses a semiconductor structure and a formation method thereof. The method comprises the steps of providing a base, wherein the base comprises a substrate and a fin portion located on the substrate, the base comprising a first region and a second region which are adjacent to each other, the fin portion stretches across the first region and the second region along an extension direction, a well region is formed in the base of the first region, and a drift region is formed in the base of the second region; forming a gate oxide layer covering the top surface and the side wall surface of the fin portion; forming a gate layer on the gate oxide layer at the junction of the first region and the second region, wherein the gate layer stretches across the fin portion and covers part of the top and part of the side wall of the fin portion; forming a source region in the well region on one side of the gate layer, and forming a drain region in the drift region on the other side ofthe gate layer; sequentially etching the gate layer, the gate oxide layer and partial thickness of the base in the drift region in part of the second region on one side of the drain region after theformation of the source region and the drain region, and forming an isolation groove in the drift region; and forming an isolation layer in the isolation groove. According to the invention, the voltage withstanding performance of the LDMOS is facilitated to be improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] As semiconductor chips are used more and more widely, there are more and more factors that cause semiconductor chips to be damaged by static electricity. In existing chip designs, electrostatic discharge (ESD, Electrostatic Discharge) protection circuits are often used to reduce chip damage. The design and application of existing ESD protection circuits include: Gate Grounded NMOS (GGNMOS for short) protection circuit, Silicon Controlled Rectifier (SCR for short) protection circuit, lateral double diffusion field Effect transistor (Lateral Double Diffused MOSFET, LDMOS for short) protection circuit, bipolar junction transistor (Bipolar Junction Transistor, BJT for short) protection circuit, etc. Among them, LDMOS is widely used in ESD protection because it can withstand a higher brea...

AI Technical Summary

Problems solved by technology

[0005] However, after the introduction of fin field effect transistors in LDMOS, the withstand voltage performance of LDMOS still needs to be improved

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