Three-dimensional memory and preparation method thereof

Abstract

The embodiment of the invention discloses a three-dimensional memory and a preparation method thereof, and the method comprises the following steps: providing a laminated structure which comprises a plurality of dielectric layers and sacrificial layers, wherein the dielectric layers and the sacrificial layers are alternately laminated, and a channel through hole CH passing through the laminated structure; forming a pre-storage layer on the side wall of the CH; removing the sacrificial layers, and exposing the pre-storage layer; and oxidizing the pre-storage layer at the position where the sacrificial layers are removed so as to form a barrier layer which is relatively close to the outer side and a storage layer which is relatively close to the inner side along the radial direction of the CH.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a three-dimensional memory and a preparation method thereof. Background technique [0002] Memory is a memory device used to save information in modern information technology. With the continuous improvement of the demand for integration and data storage density of various electronic devices, it is increasingly difficult for ordinary two-dimensional memory devices to meet the requirements. In this case, three-dimensional (3D) memory emerges as the times require. [0003] In a three-dimensional memory, the memory stack functions to control the storage of memory charges, and is the key structure for the device to complete the storage function. At present, the commonly used structure of the memory stack is barrier layer-storage layer-tunneling layer; the above layers are formed by sequential deposition in the channel hole (Channel Hole, CH); after the deposition of the above...

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Problems solved by technology

However, as the market’s requirements for storage density continue to increase, the number of three-dimensional memory stack layers continues to increase, and the aspect ratio of the CH becomes larger. The etching process of the memory stack at the bottom of the CH is facing greater challenges.

If the memory stack layer at the bottom of the CH is not removed cleanly, and the exposed surface of the channel layer of the lower selection tube is insufficient, it will cause poor contact between the channel layer and the channel layer of the lower selection tube, forming a high-resistance connection, resulting in a high threshold voltage of the three-dimensional memory. Even the current path is disconnected and the device fails

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