Buffer interface circuit and method and application for transmitting data based on circuit

Abstract

The invention provides a buffer interface circuit, comprising a first channel access control module, a second channel access control module, a channel selection register, an MUX unit, a first synchronous module, a second synchronous module, a dual-port buffer area and a peripheral access buffer area control module. One ends of the first channel access control module and the second channel access control module are correspondingly connected with the on-chip primary bus and the on-chip secondary bus respectively, and the other ends of the first channel access control module and the second channel access control module are connected with the dual-port buffer area after being selected by the MUX unit. The first channel access control module and the second channel access control module respectively carry out control information interaction with the peripheral access buffer area control module through the first synchronous module and the second synchronous module. One end of the peripheral access buffer area control module is connected with the dual-port buffer area, and the other end is connected with the peripheral module. High-efficiency data interaction between the on-chip multi-stage bus and the peripheral is achieved. Performance and efficiency are improved on the premise that correct and reliable transmission is guaranteed, and the problem of high-efficiency data transmissionbetween an internal multi-stage bus host and a peripheral interface is effectively solved.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, and relates to a buffer interface circuit and a data transmission method and application based on the circuit. Background technique [0002] In large-scale complex chips with multiple clock domains, the performance of interface circuits usually determines the data access bandwidth and system operating efficiency. Designing a high-speed interface circuit that takes into account speed, flexibility, reliability and ease of use is often the key point of chip design. [0003] The traditional buffer interface circuit is usually implemented based on fifo structure or dual-port ram structure combined with hardware control circuit. The control strategy and implementation of the hardware control circuit determine the transmission efficiency and performance of the interface buffer circuit. The traditional design usually adopts a time-sharing access strategy. The control circuits of the two clock d...

AI Technical Summary

Problems solved by technology

[0005] The present invention aims at the high-performance SoC / MCU system multi-level bus structure to high-speed peripheral multi-level access requirements, and at the same time for the situation that the buffer access efficiency is not high under the traditional time-sharing access strategy, proposes a buffer interface circuit and based on the circuit The method and application of data transmission realizes high-efficiency data interaction between on-chip multi-level buses and peripherals, improves performance and efficiency under the premise of ensuring correct and reliable transmission, and effectively solves the problem of current ultra-large-scale complex chips such as SoC. , MCU and other internal multi-level bus hosts and the problem of high-efficiency data transmission between peripheral interfaces

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