Clock frequency test circuit and measurement calculation method

Abstract

The invention relates to a clock frequency test circuit and a measurement and calculation method. The clock counting circuit comprises a clock selection circuit unit, a tested clock counting circuit unit, a reference clock counting circuit unit, a control and mark generation circuit unit and a frequency calculation circuit unit, the clock selection circuit unit comprises a control port; clock selection signals, internal clock signals and external clock signals are input into the corresponding control ports. selecting high and low levels of the signal according to the clock; the internal clocksignal and the external clock signal are mutually switched and input to the tested clock counting circuit unit; according to the clock frequency measuring circuit, frequency measurement of internal clock signals or external clock signals is achieved, frequency measurement and frequency calibration of the internal clock signals and the external clock signals are achieved, measurement errors are small, and high-precision clock frequency measurement and calculation are achieved through the clock frequency testing circuit measurement and calculation method.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a clock frequency test circuit and a calculation method. Background technique [0002] With the development of VLSI technology, the functions of ASIC or MCU also require more functions and better performance. The functions of MCU internal clock frequency calibration and external clock frequency measurement are also becoming more and more important. [0003] At present, the existing MCU internal clock frequency calibration test method generally adopts 128 frequency division output, and the tester detects the output frequency of the output port through the waveform, and then calculates the internal clock frequency. The disadvantage of this method is that the frequency of the frequency-divided clock generated is low and the error is large; at the same time, because the detection frequency of the testing machine itself is low, and the clock flip observed by the testi...

AI Technical Summary

Problems solved by technology

The disadvantage of this method is that the frequency of the generated frequency division clock is low and the error is large; at the same time, because the detection frequency of the testing machine itself is low, and the clock flip observed by the testing machine has a certain slope, the error is increased

[0004] As for the measurement of the frequency of the external clock signal, it can be realized through the counter function of the MCU combined with the internal timer function. This part requires software participation, because it needs to be combined with interrupts and instructions The execution time of delay, etc., the frequency error of its measurement is large and the measurement time is long

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