Manufacturing method for split-gate flash memory

Abstract

The invention provides a manufacturing method for a split-gate flash memory, and the method comprises the following steps: providing a semiconductor substrate, wherein a protective layer, a polycrystalline silicon material layer and a dielectric layer are sequentially formed on the semiconductor substrate; etching the dielectric layer to form a first trench; etching the polycrystalline silicon material layer in the first trench, so that the surface of the polycrystalline silicon material layer is in an arc shape; removing the remaining dielectric layer; forming a functional layer on the polycrystalline silicon material layer; etching the functional layer to form a second trench in the functional layer; and etching the polycrystalline silicon material layer in the second trench until the protective layer is exposed to form a floating gate layer, wherein a tip structure is formed at the vertex angle of the floating gate layer. The tip structure enables the electric field intensity to beimproved from the floating gate layer to a word line, so that electrons in the floating gate layer easily penetrate through the tunneling oxide layer from the tip structure to the word line through atunneling effect under an electric field with high intensity, thereby improving the tunneling effect, and improving the erasing efficiency.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a split-gate flash memory. Background technique [0002] In the development of existing memory, the split-gate flash memory has become an important non-volatile memory. The split-gate flash memory uses the floating gate layer as the storage unit, and the floating gate layer uses F-N electron tunneling and channel hot electron injection. For programming and erasing, channel hot electrons are injected into the floating gate layer during programming, and the channel is in a blocking state, which is in the state "0" at this time; when erasing, the channel is in an open state through F-N electron tunneling. This is the state "1". Split-gate flash memory is widely used for its high-efficiency programming and large-area rapid erasing and writing capabilities. [0003] Wherein, erasing refers to forming a voltage difference between the word line and th...

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Problems solved by technology

[0004] The object of the present invention is to provide a method for manufacturing split-gate flash memory, to solve the problem of unsatisfactory erasing performance of split-gate flash memory

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