3D memory device and manufacturing method thereof

Abstract

The application discloses a 3D storage device and a manufacturing method thereof. The 3D memory device includes: a substrate; a gate stack structure located above the substrate, the gate stack structure including a plurality of gate conductors and a plurality of interlayer insulating layers stacked alternately; penetrating through the gate stack A plurality of channel pillars of a structure, the plurality of channel pillars comprising: a core including a fill layer containing a passivation element; a channel layer surrounding the core, the channel layer containing the passivation elements. In the 3D memory device, since the filling layer is located inside the channel pillar, the passivation element can diffuse in the channel layer of the corresponding channel pillar. Compared with the technical solution of setting the passivation element source outside the channel, it avoids the problem that the passivation element cannot be effectively diffused to the channel layer due to the back-end line and the stacked structure blocking the diffusion of the passivation element, thereby improving Yield and reliability of 3D memory devices.

Description

technical field [0001] The present invention relates to memory technology, and more particularly, to 3D memory devices and manufacturing methods thereof. Background technique [0002] The improvement of the storage density of the memory device is closely related to the progress of the semiconductor manufacturing process. As the feature size of the semiconductor manufacturing process becomes smaller and smaller, the storage density of the memory device becomes higher and higher. In order to further increase storage density, memory devices with a three-dimensional structure (ie, 3D memory devices) have been developed. A 3D memory device includes a plurality of memory cells stacked in a vertical direction, which can double the integration level on a wafer per unit area and reduce the cost. [0003] Existing 3D memory devices are mainly used as non-volatile flash memory. The two main non-volatile flash memory technologies use NAND and NOR structures, respectively. Compared w...

AI Technical Summary

Problems solved by technology

In the prior art, PE-SiN is formed on the surface of the semiconductor structure as a source of passivation elements to passivate the channel layer, and the passivation elements need to be diffused into the trench through the back end line (Back End of the Line, BEOL) and the stacked structure. channel layer, there will be a problem that passivation elements cannot diffuse into the channel layer

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