A chip security monitoring method and a security monitoring chip

Abstract

The invention discloses a chip safety monitoring method and a safety monitoring chip. The method comprises the following steps: a monitor embedded in the chip monitors the chip operation; Wherein themonitor comprises a first state machine corresponding to a model established by a known chip attack and / or a second state machine converted from a security rule / security attribute described by an assertion. The monitor of the invention covers both known attack modes and unknown attack modes that can be excluded by security attributes. Especially the monitor based on security attributes, because ofthe expressive power of assertion language, the security attributes will be very inclusive, and the chip design does not need complex and time-consuming security attributes verification, and also avoids the possible performance loss caused by filling security loopholes.

Description

technical field [0001] The invention relates to the field of chip security, in particular to a chip security monitoring method and a security monitoring chip. Background technique [0002] Chip security has attracted widespread attention in the information industry recently. The Specter and Meltdown exploits, which were discovered in early 2018, exploit the branch prediction and out-of-order execution commonly used in chip design to perform high-speed reading of highly confidential memory information, seriously threatening a variety of processors from Intel, AMD, and ARM. [0003] Chip security risks can be discovered and eliminated by using targeted verification methods in the design process, but there are two major disadvantages in doing so: first, the complexity of chip design is increasing, and the integrity of verification cannot be guaranteed; second, many chip security The vulnerability itself is the result of chip performance optimization, such as the aforementioned...

AI Technical Summary

Problems solved by technology

[0003] Chip security risks can be discovered and eliminated by using targeted verification methods in the design process, but there are two major disadvantages in doing so: first, the complexity of chip design is increasing, and the integrity of verification cannot be guaranteed; second, many chip security The vulnerability itself is the result of chip performance optimization, such as the aforementioned branch prediction and out-of-order execution

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