Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

NMOS transistor and manufacturing method thereof

A manufacturing method and pseudo gate technology, which can be used in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., and can solve problems such as the impact of device performance stability

Inactive Publication Date: 2019-03-15
SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD
View PDF5 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] With the development of technology, the critical dimension (CD) of the device is getting smaller and smaller. For example, the technology node of the existing HKMG process, that is, the CD has reached below 28nm, which makes the short channel effect of the device more and more serious. , so that the performance of the device such as the stability of the device is seriously affected

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • NMOS transistor and manufacturing method thereof
  • NMOS transistor and manufacturing method thereof
  • NMOS transistor and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0045] The manufacturing method of the existing NMOS tube:

[0046] Before introducing the embodiment of the present invention in detail, introduce the manufacturing method of the existing NMOS tube, such as Figure 1A to Figure 1B Shown is a device structure diagram in each step of the manufacturing method of the existing NMOS tube; the manufacturing method of the existing NMOS tube includes the following steps:

[0047] Step 1, such as Figure 1A As shown, a silicon substrate with a P well 101 formed on its surface is provided, a dummy gate structure is formed on the surface of the P well 101 , and a channel 103 is formed on the surface of the P well 101 covered by the dummy gate structure.

[0048] The dummy gate structure includes a first gate dielectric layer and a polysilicon dummy gate 102 formed on the surface of the P well 101 .

[0049] Silicon nitride spacers are formed on both sides of the dummy gate structure.

[0050] Step two, such as Figure 1A As shown, si...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses an NMOS transistor. A manufacturing method of the NMOS transistor comprises the following steps: a P well is formed on the surface of a silicon substrate; a gate structure is formed on the surface of the P well; grooves are formed in the two sides of the gate structure; embedded epitaxial layers are arranged in the grooves; the embedded epitaxial layers include a silicon seed layer, a silicon-phosphorus body layer, a dual barrier layer located between the silicon-phosphorus body layer and the silicon seed layer, and a silicon cap layer protruding to the tops of the grooves; the dual barrier layer is formed by superposing a first barrier layer and a second barrier layer which are different in material; the silicon-phosphorus body layer has a phosphorus-heavily-dopedstructure; and the dual barrier layer is used for reducing the number of phosphorus of the embedded epitaxial layers, externally extending into the P well on the circumferential side, so as to reduceand prevent the influence of the externally-expanded phosphorus on a channel. The invention further discloses the manufacturing method of the NMOS transistor. The short channel effect of a device canbe improved, so that the stability of the device can be improved.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to an NMOS tube; the invention also relates to a manufacturing method of the NMOS tube. Background technique [0002] HKMG has a gate dielectric layer with a high dielectric constant (HK) and a metal gate (MG), so it is usually abbreviated as HKMG in the art. In MOS transistors using HKMG, the source and drain regions of NMOS often use embedded epitaxial layers. The material of the embedded epitaxial layers of NMOS is usually SiP. The stress of the channel region of NMOS is changed by the embedded epitaxial layer and the formation is beneficial. The tensile stress that improves the mobility of electrons in the channel region of the NMOS can improve the mobility of electrons in the channel region of the NMOS and reduce the channel resistance. [0003] With the development of technology, the critical dimension (CD) of the device is getting smaller and sma...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/06H01L29/26H01L29/41H01L29/423H01L21/336
CPCH01L29/0692H01L29/26H01L29/41H01L29/42316H01L29/66409
Inventor 陈品翰
Owner SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products