Transmission delay test method and device based on FPGA

A technology of transmission delay and test method, applied in the field of communication, can solve the problems of large safety margin of maximum transmission delay information, and FPGA chip cannot give full play to its performance, so as to reduce the design margin and improve the accuracy.

Active Publication Date: 2019-01-15
SHENZHEN PANGO MICROSYST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The present invention provides a transmission delay testing method and device based on FPGA to solve the problems caused by the fact that the maximum transmission delay information obtain

Method used

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  • Transmission delay test method and device based on FPGA
  • Transmission delay test method and device based on FPGA
  • Transmission delay test method and device based on FPGA

Examples

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Embodiment 1

[0051] In order to solve the defect in the prior art that the maximum transmission delay information obtained by simulation based on the worst conditions has a larger safety margin than the actual one, which causes the FPGA chip to fail to fully utilize its performance, this embodiment provides a FPGA-based transmission delay test method, such as figure 1 Shown is the basic flowchart of the FPGA-based transmission delay testing method provided in this embodiment, and the transmission delay testing method specifically includes the following steps:

[0052] S101. Drive the first D flip-flop through the first clock to alternately output low-level signals and high-level signals, and drive the second D flip-flop through the second clock to receive signals output by the first D flip-flop; The period of the first clock is T1, the period of the second clock is T2, and T1 is greater than T2.

[0053] Specifically, in this embodiment, two clocks with different periods are input, and th...

Embodiment 2

[0070] In order to better understand the present invention, the present embodiment illustrates the FPGA-based transmission delay testing method with a specific example, image 3 The detailed flowchart of the FPGA-based transmission delay test method provided by the second embodiment of the present invention, the transmission delay test method includes:

[0071] S301. Drive the first D flip-flop through the first clock to alternately output the low-level signal and the high-level signal, and drive the second D flip-flop through the second clock to receive the signal output by the first D flip-flop; The period of the first clock is T1, the period of the second clock is T2, and T1 is greater than T2.

[0072] In this embodiment, two clocks with different periods are input, and the absolute value of the difference between the periods of these two clocks is also the transmission delay test accuracy in this embodiment, wherein the period T1 of the first clock CLK1 is relatively larg...

Embodiment 3

[0088] This embodiment provides a FPGA-based transmission delay testing device, for details, please refer to Figure 4 , including: a first clock 41, a second clock 42, a first D flip-flop 43, a second D flip-flop 44, a counter 45, an edge synchronization detection unit 46 and a signal reception determination unit 47, the first D flip-flop 43 and the second D flip-flop The path 48 to be tested is connected between the two D flip-flops 44; the Q port of the first D flip-flop 43 is connected back to the D port through an inverter, the cycle of the first clock 41 is T1, and the cycle of the second clock 42 is T2, T1 Greater than T2; the first clock 41 is used to drive the first D flip-flop 43 to alternately output low-level signals and high-level signals; the second clock 42 is used to drive the second D flip-flop 44 to perform the first D flip-flop 43 The reception of the output signal; the edge synchronous detection unit 46 is used to determine the moment when the effective clo...

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Abstract

The invention provides a transmission delay test method and a transmission delay test device based on FPGA. Two clock phases that are constantly tightening are simulated by two different cycles of clocks. and an edge synchronization detection unit determines the time at which the effective clock edges of the two clocks are aligned, and the signal reception determination unit determines the time when the fast clock cannot acquire the slow clock signal, A phase difference between the two clocks is then calculated based on the number counted by the counter in the time interval between the alignment of the two clock valid clock edges to the acquisition of the slow clock signal by the fast clock, Then the transmission delay of the circuit to be tested is determined by the phase difference and the period of the slow clock, which effectively improves the accuracy of the transmission delay test, so that the user can reasonably reduce the design margin in the FPGA application, and can give fullplay to the performance of the FPGA chip.

Description

technical field [0001] The invention relates to the technical field of communications, in particular to an FPGA-based transmission delay testing method and device. Background technique [0002] Field Programmable Gate Array FPGA (Field Programmable Gate Array) is a semiconductor device, including some reprogrammable logic modules inside, mainly including the following three parts: configurable logic module CLB (configurable logic block), input and output Module IOB (input / output block) and programmable interconnect (programmable interconnect). FPGA uses a hardware description language (such as Verilog) for circuit design, and then generates a bit stream file containing all programmable logic module configuration information through EDA software, downloads this bit stream to the configuration memory unit inside the FPGA, and completes the CLBs, IOBs And the configuration of programmable interconnection lines, etc., is the mainstream technology of modern IC design verificatio...

Claims

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Application Information

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IPC IPC(8): H04B17/309H04L12/26H04L7/00H04J3/06
CPCH04J3/0638H04L7/00H04L43/0852H04B17/309
Inventor 田永杰
Owner SHENZHEN PANGO MICROSYST CO LTD
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