Transmission delay test method and device based on FPGA

Abstract

The invention provides a transmission delay test method and a transmission delay test device based on FPGA. Two clock phases that are constantly tightening are simulated by two different cycles of clocks. and an edge synchronization detection unit determines the time at which the effective clock edges of the two clocks are aligned, and the signal reception determination unit determines the time when the fast clock cannot acquire the slow clock signal, A phase difference between the two clocks is then calculated based on the number counted by the counter in the time interval between the alignment of the two clock valid clock edges to the acquisition of the slow clock signal by the fast clock, Then the transmission delay of the circuit to be tested is determined by the phase difference and the period of the slow clock, which effectively improves the accuracy of the transmission delay test, so that the user can reasonably reduce the design margin in the FPGA application, and can give fullplay to the performance of the FPGA chip.

Description

technical field [0001] The invention relates to the technical field of communications, in particular to an FPGA-based transmission delay testing method and device. Background technique [0002] Field Programmable Gate Array FPGA (Field Programmable Gate Array) is a semiconductor device, including some reprogrammable logic modules inside, mainly including the following three parts: configurable logic module CLB (configurable logic block), input and output Module IOB (input / output block) and programmable interconnect (programmable interconnect). FPGA uses a hardware description language (such as Verilog) for circuit design, and then generates a bit stream file containing all programmable logic module configuration information through EDA software, downloads this bit stream to the configuration memory unit inside the FPGA, and completes the CLBs, IOBs And the configuration of programmable interconnection lines, etc., is the mainstream technology of modern IC design verificatio...

AI Technical Summary

Problems solved by technology

[0005] The present invention provides a transmission delay testing method and device based on FPGA to solve the problems caused by the fact that the maximum transmission delay information obtained by simulation based on the worst conditions in the prior art has a larger safety margin than the actual one. The technical problem that the FPGA chip cannot give full play to the performance

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