Low-cost miniature narrow pulse generating method

Abstract

The present invention relates to a low-cost miniature narrow pulse generating method, and an employed circuit comprises an excitation source for generating a PWM excitation signal, a delay line moduleand an exclusive OR gate comparator. The method is characterized in that according to the required pulse width of the narrow pulse, the delay parameter of the delay line module is determined, and thePWM excitation signal is used as the original signal; the delay signal of the delay line module and the original signal pass through the exclusive XOR gate comparator to obtain a narrow pulse signalwhich is finally outputted. The method has the advantages of low cost and good stability.

Description

technical field [0001] The invention belongs to the field of electronic technology and relates to a low-cost and miniaturized narrow pulse generation method. Background technique [0002] Narrow pulse signals are widely used in many fields, such as pulsed laser drive, step test, etc., and the pulse width is mostly at ns level or below. The traditional narrow pulse methods include thyratrons, avalanche tube arrays and high-speed switches, etc., but the pulse waveforms obtained by these methods are not good, the harmonics are large, and some voltage amplitudes are extremely high, which are only suitable for driving laser devices. The suitability is not high. At the same time, there are also digital methods, such as using FPGA and CPLD to generate pulse waveforms, or using gate circuits to compete and take risks. However, FPGA is expensive and has a large package, so it has no advantages in applications with fewer channels and high volume requirements; CPLD requires a higher ...

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Problems solved by technology

However, FPGA is expensive and has a large package, so it has no advantages in applications with fewer channels and high volume requirements; CPLD requires a higher frequency of crystal oscillator because it does not have a built-in phase-locked loop, and it has fewer channels than FPGA. There is no advantage in applications with high volume requirements; the scheme of gate circuit competition and risk has the disadvantages of poor pulse time stability, repeatability and interchangeability because the pulse width depends on the delay time of the gate circuit

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