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Test system, method and device

A test system and test signal technology, applied in the direction of measurement device, measurement of electricity, measurement of electric variables, etc., can solve the problems of long calibration time, complex test system, low test efficiency, etc., to achieve low test cost, reduce test process, The effect of improving test efficiency

Inactive Publication Date: 2018-11-27
ANALOGIX CHINA SEMICON +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The embodiment of the present invention provides a test system, test method and device, to at least solve the technical problem of low test efficiency due to the complexity of the test system and long calibration time in the related art

Method used

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  • Test system, method and device

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Experimental program
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Effect test

Embodiment 1

[0034] Optionally, the programmable gate array (such as XC7Z030) in the present invention may also include an embedded ARM processor, which can realize software control of the entire pre-test system.

[0035] Therefore, in the present invention, the programmable gate array is used to generate the test signal and the interference signal at the same time, so as to realize the performance detection of the device to be tested. After the device under test receives the signal, if it is judged that the signal is consistent with the preset test signal, it means that the device under test receives the signal successfully. If not, it means that the device under test fails to receive the signal this time.

[0036] For the actual physical layer test of the receiving end of the device under test, it can be divided into pre-test and formal test. The pre-test is responsible for confirming whether the device under test supports the basic process of physical layer testing, as well as the recep...

Embodiment 2

[0051] image 3 is a schematic diagram of another optional test system according to an embodiment of the present invention, such as image 3 As shown, the test system includes: computer (corresponding to the above-mentioned external machine terminal equipment), FPGA XC7Z030 (corresponding to the above-mentioned programmable gate array FPGA), flash memory (can be falsh flash memory), serial port to USB, bridge module (as Signal transmission module), DC-DC power supply, DisplayPort receiving end equipment under test.

[0052] In the embodiment of the present invention, a Xilinx FPGA XC7Z030 is used as a main link generator and an auxiliary controller. XC7Z030 can have four sets of independent high-speed serial transceivers GTX, and each set can support a maximum transmission rate of 12.5Gbps. Currently, the maximum transmission rate of the DisplayPort standard is 8.1Gbps. XC7Z030 can fully support all current DisplayPort transmission rates. In terms of quantity, it can also ...

Embodiment 3

[0064] According to an embodiment of the present invention, an embodiment of a testing method is provided. It should be noted that the steps shown in the flow charts of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and, although in The flowcharts show a logical order, but in some cases the steps shown or described may be performed in an order different from that shown or described herein.

[0065] Figure 5 It is a flowchart of a test method according to an embodiment of the present invention, which is applied to any of the above test systems, such as Figure 5 As shown, the method includes the following steps:

[0066] Step S102, detecting whether a test instruction triggered by a test operation is received.

[0067] Step S104, after receiving the test instruction, determine the target link rate and the target channel.

[0068] Step S106, according to the target link rate and the target channel, send a tes...

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Abstract

The invention discloses a test system, method and device. The test system comprises a preset field programmable gate array FPGA and a Display Port receiving-end device to be tested, and the FPGA supports signal reception and transmission of multiple links. The test method comprises that whether a test instruction triggered by a test operation is received is detected; after that the test instruction is received, a target main link is selected from the multiple links by the FPGA, and used to send a test signal to the Display Port receiving-end device to be tested, and when the Display Port receiving-end device to be tested receives the test signal, whether the test signal is consistent with a target test signal is determined by comparison, and a comparison result is obtained; the FPGA obtains the comparison result; and whether a test operation succeeds is determined according to the comparison result. Thus, the technical problem that the test efficiency is relatively low due to the factthat the test system is complex and calibration time is long in related art is solved.

Description

technical field [0001] The invention relates to the technical field of chip testing, in particular to a testing system, testing method and device. Background technique [0002] DisplayPort (DisplayPort) is one of the current mainstream high-speed digital video interfaces. DisplayPort is mainly used in the connection and communication between the host computer and the display. Currently, the highest data link rate it can support can reach 8.1Gbps / s (single channel) , if multiple communication channels are used for communication at the same time, the communication rate at this time will be very high. Such a high-speed interface is not small for the operation of sending-end chips, cables, connectors, PCBs, and receiving-end chips. challenge. Therefore, DisplayPort-related products need to carry out some physical layer and link layer tests to measure whether the product meets the requirements of the protocol. Among them, the test of the physical layer is the most important par...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/00
CPCG01R31/00
Inventor 文其林
Owner ANALOGIX CHINA SEMICON
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