Testing method and system of standard cell library full model

Abstract

The invention provides a testing method of a standard cell library full model. The testing method comprises the following steps that 201, multiple physical rule checking is conducted on standard celllayout; 202, form verification of a standard cell library model is performed; 203, Benchmark electrical properties of a standard cell library are verified; 204, chip design silicon verification of thestandard cell library is performed. The invention provides a testing system of the standard cell library full model. Testing verification of the standard cell library full model can be quickly completed at high coverage rate.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, in particular to the field of integrated circuit design automation, and specifically relates to a test method and a test system for a full model of a standard cell library. Background technique [0002] The standard cell library is a collection of basic logic cells developed based on a mature and stable process. Each standard cell library has hundreds to thousands of cells, and the cell types are very rich, including basic cells, combinational logic cells, sequential logic cells, and special cells. The standard cell library is the basic database for VLSI (Very Large Scale Integration) automatic design. Its database model is rich, including cell simulation library, cell symbol, cell layout, logic function model, timing synthesis library model, and cell netlist. , layout and routing library and other data. like figure 1 As shown, a full set of standard cell library models supports the en...

AI Technical Summary

Problems solved by technology

The disadvantages of adopting this method are as follows: 1. The physical design rule check of the standard cells is completed one by one, but the standard cells in the actual chip are randomly spliced ​​together, and the existing verification method is not perfect in the verification of the cell splicing.

2. Design process verification can ensure the correctness of various library model data formats, but cannot guarantee the consistency between various library model data

3. A single chip design cannot guarantee the electrical characteristics of the standard cell library

After the standard cell library with incomplete verification is released, potential library model data errors or information differences between models will directly affect the application of chip designers, and even lead to chip tape-out failures

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