A Method for Improving Control Gate Filling Defects

Abstract

The invention discloses a method for improving control gate filling defects. Polysilicon is deposited at a lower temperature on the surface of a semiconductor structure with a floating gate structure to form a polysilicon layer, and then the silicon wafer is subjected to high-temperature annealing treatment to make the polysilicon secondary grow. By adopting the technical solution of the invention, void defects during filling of polysilicon can be eliminated, while the resistance value of polysilicon and the mobility of carriers are kept unchanged, meeting the process requirements.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for improving control gate filling defects. Background technique [0002] In the existing manufacturing process of semiconductor memory, the process of forming a control gate on the wafer surface is included. In an existing process for forming a control gate, a polysilicon deposition process under high temperature conditions is usually used. However, polysilicon not only has a faster deposition rate but also has a larger grain size under high temperature conditions. Therefore, the polysilicon deposited in the high-aspect-ratio floating gate space in the existing process will form voids, resulting in a decrease in the contact area between the control gate and the floating gate, and ultimately affecting the coupling rate of the device. [0003] As the device size gradually decreases, the opening of the trench between the floating gates becomes smaller and small...

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Problems solved by technology

However, this approach will reduce the particle size of polysilicon, resulting in a reduction in the grain boundaries of polysilicon, reducing the mobility of carriers, and increasing the resistance of polysilicon. Therefore, the existing improved process also has relatively large defects.

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