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FPGA-based network function acceleration method and system

A technology for network functions and acceleration systems, applied in the field of data processing, can solve the problems of high CPU core occupancy, low resource utilization, low throughput, etc. Effect

Active Publication Date: 2018-07-24
HUAZHONG UNIV OF SCI & TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Aiming at the deficiencies of the prior art, the present invention provides an FPGA-based network function acceleration method and system, which effectively solves the problem of high CPU core occupancy, low throughput, and the actual resources of the FPGA in the prior art. The problem of underutilization

Method used

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  • FPGA-based network function acceleration method and system

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Embodiment 1

[0041] This embodiment discloses an FPGA-based network function acceleration method and system. In the case of no conflict or contradiction, preferred implementation manners of other embodiments may serve as supplements to this embodiment.

[0042] The present invention provides a network function acceleration method based on FPGA, the method comprising: constructing a network function acceleration system, the system includes a physical machine A and an accelerator card B, the physical machine A and the accelerator card B are connected through a PCIe channel, and the physical machine A Including a processor, the accelerator card B includes an FPGA, and the accelerator card B is used to provide network function acceleration for the processor; the processor is configured to: when the accelerator card is required to provide network function acceleration, query whether the required acceleration already exists in the FPGA module, if yes, obtain the acceleration function ID correspo...

Embodiment 2

[0054] This embodiment is a further improvement on Embodiment 1, and repeated content will not be repeated here. In the case of no conflict or contradiction, preferred implementation manners of other embodiments may serve as supplements to this embodiment.

[0055] According to a preferred embodiment, referring to Fig. 2, the method of the present invention may include: step S100, constructing a network function acceleration system, the system may include a physical machine A and an acceleration card B, and the physical machine A and the acceleration card B are connected through a PCIe channel , the accelerator card B includes FPGA. Preferably, the physical machine A may be provided with an acceleration function management module A3. Preferably, the acceleration function management module A3 may be a virtual machine running on the physical machine A. Alternatively, the acceleration function management module A3 may be independent hardware connected to the physical machine A ...

Embodiment 3

[0081] This embodiment is a further improvement on Embodiments 1 and 2 or their combination, and repeated content will not be repeated here. In the case of no conflict or contradiction, preferred implementation manners of other embodiments may serve as supplements to this embodiment.

[0082] According to a preferred embodiment, the method of the present invention may further include: the acceleration function management module A3 associates the required acceleration module with the corresponding network function module A2.

[0083] According to a preferred embodiment, the network function module A2 is a software program that runs on the physical machine A and is independent of each other. For example, a virtual machine. The network function module A2 may include a general processing unit A21 and a computation-intensive unit A22. Preferably, different network function modules A2 have their own independent common processing unit A21 and computation-intensive unit A22. The da...

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Abstract

The invention relates to an FPGA-based network function acceleration method and system. The method comprises the steps of establishing the network function acceleration system. The system comprises aphysical machine and an acceleration card. The physical machine is connected with the acceleration card through a PCIe channel. The physical machine comprises a processor. The acceleration card comprises an FPGA and is used for providing network function acceleration for the processor. The processor is configured to query whether a required acceleration module exists in the FPGA or not when the acceleration card is needed to provide the network function acceleration, if yes, obtain an acceleration function ID corresponding to the required acceleration module, if not, select at least one partial reconfiguration region in the FPGA, configure the region as the required acceleration module and generate the corresponding acceleration function ID, and / or send an acceleration request to the FPGA,wherein the acceleration request comprises a to-be-processed data package and the acceleration function ID. The FPGA is configured to send the acceleration request to the required acceleration modulefor performing acceleration processing according to the acceleration function ID.

Description

technical field [0001] The invention relates to the field of data processing, in particular to an FPGA-based network function acceleration method and system. Background technique [0002] With the development of software-defined networks, in order to improve the flexibility of network data plane processing, software-based network function processing applications on traditional X86 servers are gradually becoming popular. Compared with the traditional network middleware (MiddleBox) based on dedicated hardware, the software-based network function has the characteristics of flexibility, low cost, and easy deployment. [0003] At present, the network bandwidth in the data center is generally 10Gbps-40Gbps, and some are even as high as 100Gbps. On a 10Gbps data link, in order to achieve the maximum throughput rate, in the case of a data packet with a size of 64Byte, it takes 67.2ns to process a data packet. Software-based network function applications rely on the CPU to process ...

Claims

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Application Information

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IPC IPC(8): G06F13/40G06F13/42
CPCG06F13/4009G06F13/4221G06F9/45558G06F9/5027G06F15/7871G06F2009/45595G06F2209/509G06F15/7867
Inventor 刘方明金海李肖瑶
Owner HUAZHONG UNIV OF SCI & TECH
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