Control circuit for converting asynchronous interface into synchronous interface

Abstract

The invention discloses a control circuit for converting an asynchronous interface into a synchronous interface and relates to the technical field of integrated circuits. According to the control circuit, through combination of a reading clock detection unit, a writing clock detection unit, a first monostable unit, a second monostable unit and a delay control unit, conversion from the asynchronousinterface into the synchronous interface is realized, synchronous transmission of data is completed, communication between the external asynchronous interface and a local synchronous circuit is realized, conversion is completed in one cycle, signal conversion efficiency is improved, and a metastable state is avoided.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an asynchronous interface-to-synchronous interface control circuit. Background technique [0002] An asynchronous interface is an interface that does not require a clock signal for data transmission. Taking the asynchronous random access memory interface as an example, it includes a chip select control terminal, a write control terminal, a read control terminal, an address terminal, and a data terminal. [0003] The synchronous interface is an interface for data transmission through the clock signal. All operations sample the interface signal at the edge of the clock. Taking the synchronous random access memory interface as an example, it includes the clock terminal, the chip selection control terminal, the write control terminal, the output control terminal, and the address terminal. and data terminal. [0004] At present, in order to avoid the metastable state of t...

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Problems solved by technology

[0004] At present, in order to avoid the metastable state of the system, it is generally necessary to provide a clock signal for two cycles of synchronous sampling when converting an asynchronous interface to a synchronous interface, resulting in the asynchronous signal not being able to complete sampling in a single cycle, and the conversion efficiency is low.

In the case that a single cycle is required to convert an asynchronous interface to a synchronous interface, the system does not provide a clock signal, and the current commonly used clock signal cannot be used to synchronize two cycles.

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