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Split-gate flash memory unit and preparation method thereof

A flash memory cell, split gate technology, applied in the field of memory, can solve problems such as floating gate and word line coupling, and achieve the effects of reducing leakage, improving erasing performance, and reducing coupling

Active Publication Date: 2018-05-29
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to provide a split-gate flash memory unit and its preparation method to solve the technical problem of coupling between the floating gate and the word line in the prior art

Method used

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  • Split-gate flash memory unit and preparation method thereof

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Embodiment Construction

[0036] The split-gate flash memory unit of the present invention and the schematic diagram of the manufacturing method thereof will be described in more detail below in conjunction with schematic diagrams, wherein a preferred embodiment of the present invention is shown, and it should be understood that those skilled in the art can modify the present invention described herein, while still The advantageous effects of the present invention are realized. Therefore, the following description should be understood as the broad knowledge of those skilled in the art, but not as a limitation of the present invention.

[0037] In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions and constructions are not described in detail since they would obscure the invention with unnecessary detail. It should be appreciated that in the development of any actual embodiment, numerous implementation details must be ...

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Abstract

The invention relates to a split-gate flash memory unit and a preparation method thereof. The preparation method comprises the following steps that: a plurality of flash memory transistors are formedon a semiconductor substrate, wherein each flash memory transistor comprises a floating gate, a storage dielectric layer, a control gate and a sidewall, wherein the floating gate, the storage dielectric layer and the control gate are located on the bottom surface of the semiconductor substrate, and the sidewall is located at one side of the control gate and the storage dielectric layer; a sacrificial oxide layer is formed on the opposite sidewalls and bottom wall of two adjacent flash memory transistors; the sacrificial oxide layer located on the bottom wall is partially removed; a polycrystalline silicon layer is formed on the exposed surface of the semiconductor substrate; and a tunneling oxide layer and a word line polycrystalline layer are formed on the surface of the polycrystalline layer. With the split-gate flash memory unit and the preparation method thereof of the present invention adopted, coupling between word lines and the floating gates can be reduced, erasure performancecan be improved, and leakage current can be reduced.

Description

technical field [0001] The invention relates to the field of memory technology, in particular to a split-gate flash memory unit and a preparation method thereof. Background technique [0002] In the current semiconductor industry, integrated circuit products can be mainly divided into three types: analog circuits, digital circuits and digital / analog hybrid circuits, among which storage devices are an important type of digital circuits. Among storage devices, the development of flash memory (flash memory for short) is particularly rapid in recent years. The main feature of flash memory is that it can keep stored information for a long time without power on; and it has the advantages of high integration, fast access speed, easy erasing and rewriting, etc., so it has been widely used in many fields such as microcomputer and automatic control. a wide range of applications. [0003] The standard physical structure of flash memory is called a memory cell (bit). The structure of...

Claims

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Application Information

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IPC IPC(8): H01L27/11521
CPCH10B41/30
Inventor 刘宪周
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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