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Configuring coarse-grained reconfigurable arrays (CGRAs) for dataflow instruction block execution in block-based dataflow instruction set architectures (ISAs)

A technology of instruction set architecture and data flow, applied in the direction of concurrent instruction execution, data flow computer, architecture with a single central processing unit, etc., can solve the problem that the program cannot be executed by the computer processor.

Inactive Publication Date: 2018-05-11
QUALCOMM INC
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Problems solved by technology

Therefore, a program that has been compiled for processing using CGRA cannot be executed on a computer processor that does not provide CGRA

Method used

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  • Configuring coarse-grained reconfigurable arrays (CGRAs) for dataflow instruction block execution in block-based dataflow instruction set architectures (ISAs)
  • Configuring coarse-grained reconfigurable arrays (CGRAs) for dataflow instruction block execution in block-based dataflow instruction set architectures (ISAs)
  • Configuring coarse-grained reconfigurable arrays (CGRAs) for dataflow instruction block execution in block-based dataflow instruction set architectures (ISAs)

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Embodiment Construction

[0017] Referring now to the figures, several exemplary aspects of the invention are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0018] Aspects disclosed in the detailed description include configuring a coarse-grained configurable array (CGRA) in a block-based dataflow instruction set architecture (ISA) for dataflow instruction block execution. In one aspect, the CGRA configuration circuit is provided in a block-based dataflow ISA. The CGRA configuration circuit is configured to dynamically configure the CGRA to provide the functionality of the data flow instruction block. A CGRA includes an array of tiles, each of which provides functional units and switches. The instruction decoding circuitry of the CGRA configuration circuit maps each data flow instruction within a data flow instruc...

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Abstract

Configuring coarse-grained reconfigurable arrays (CGRAs) for dataflow instruction block execution in block-based dataflow instruction set architectures (ISAs) is disclosed. In one aspect, a CGRA configuration circuit is provided, comprising a CGRA having an array of tiles, each of which provides a functional unit and a switch. An instruction decoding circuit of the CGRA configuration circuit mapsa dataflow instruction within a dataflow instruction block to one of the tiles of the CGRA. The instruction decoding circuit decodes the dataflow instruction, and generates a function control configuration for the functional unit of the mapped tile to provide the functionality of the dataflow instruction. The instruction decoding circuit further generates switch control configurations for switchesalong a path of tiles within the CGRA so that an output of the functional unit of the mapped tile is routed to each tile corresponding to consumer instructions of the dataflow instruction.

Description

[0001] priority claim [0002] This application claims the application titled "CONFIGURING COARSE-GRAINEDRECONFIGURABLE IN A BLOCK-BASED DATA FLOW INSTRUCTION SET ARCHITECTURE (ISA) FOR CONFIGURING COARSE-GRAINEDRECONFIGURABLE ARRAYS (CGRAs) FOR DATAFLOW INSTRUCTION BLOCK EXECUTION INBLOCK-BASED DATAFLOW INSTRUCTION SET ARCHITECTURES (ISAs)" is of priority to US Patent Application No. 14 / 861,201, the contents of which are incorporated herein by reference in their entirety. technical field [0003] The techniques of this disclosure generally relate to the execution of blocks of dataflow instructions in a computer processor core according to a block-based dataflow instruction set architecture (ISA). Background technique [0004] Modern computer processors consist of functional units that perform operations and calculations, such as addition, subtraction, multiplication and / or logical operations, for the execution of computer programs. In conventional computer processors, the...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/78G06F15/82G06F9/30G06F9/38G06F9/44
CPCG06F15/7892G06F15/825G06F9/30181G06F9/3836G06F9/3897G06F9/4494G06F9/3858G06F15/7867
Inventor K·桑卡拉林加姆G·M·赖特
Owner QUALCOMM INC
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