Interconnection interface test method and device and computing equipment

Abstract

The invention discloses an interconnection interface test method. The method comprises the steps that a first test device acquires a CC request message from a test mapping table; a second test deviceis determined according to a memory address, and the CC request message is sent to the second test device through an interconnection interface; a CC response message returned by the second test deviceaccording to the CC request message is received through the interconnection interface; and an expected response message associated with the CC request message is queried according to the test mappingtable, and when the expected response message is matched with the CC response message, it is determined that the interconnection interface of an associated first processor passes testing. The embodiment of the invention furthermore discloses computing equipment, a test device and a BIOS. By the adoption of the calculation scheme, the interconnection interface can be tested under the condition ofnot starting an operating system, test completeness is improved, and processing overhead of the processor is lowered.

Description

technical field [0001] The invention relates to the field of testing, in particular to a testing method, device and computing equipment for an interconnection interface. Background technique [0002] With the continuous development of integrated circuit production technology, the integration of processor chips is getting higher and higher, and multiple processors can be integrated on-chip to form a multi-processor system. Through a specially designed interconnection bus, multiple processors Realize point-to-point communication to increase the transfer rate between processors. Typical interconnect buses include a QPI (QuickPath Interconnect, QuickPath Interconnect) bus and an HT (HyperTransprot, HyperTransport) bus. [0003] The current interconnection bus mainly includes protocol layer, routing layer, link layer and physical layer. [0004] The protocol layer (Protocol Layer) is mainly used to maintain the cache coherence (Cache Coherency) of each processor in the multipro...

AI Technical Summary

Problems solved by technology

[0008] In order to ensure the reliability of the multi-processor system, it is necessary to test the interconnection interface of the multi-processor. The current test method used in the industry usually tests the physical layer and link layer of the interconnection interface in sequence after the operating system is started. However, The problem with the current test method is that the processor is tested during operation, which will cause the processor load to be too high. At the same time, the behavior of the processor cannot be precisely controlled, so that it cannot cover all test scenarios, and the test is not complete.

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