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3D memory and preparation method thereof

A memory, three-dimensional technology, applied in the direction of semiconductor devices, electrical solid-state devices, electrical components, etc., to achieve the effect of improving device performance

Active Publication Date: 2018-03-30
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In order to solve the above-mentioned technical problems, the present invention provides a three-dimensional memory and its preparation method, to solve the problem that the first dielectric layer closest to the substrate of the stacked structure constituting the step region reacts with the substrate in the subsequent process, so that the Problems with the formation of unnecessary oxidative structures in the

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Embodiment Construction

[0048] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0049] The embodiment of the present application provides a method for preparing a three-dimensional memory, such as image 3 shown, including:

[0050]S101: Provide a substrate, the surface of the substrate has multiple stacked structures, the multiple stacked structures are respectively located on the array area of ​​the substrate and the surface of two step areas, and the two step areas are respectively located on the surface of the array On both sides of ...

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Abstract

The application discloses a 3D memory and a preparation method thereof. According to the preparation method of the 3D memory, after stack structures located in an array area and a step area are formedon the surface of a substrate, a protective film is formed on the surface of the stack structure in the step area, and the protective film is etched. In the etching process, after the etching of theprotective film on the other steps is completed, part of the protective film on the sidewall of the step nearest to the substrate is still retained. The retained part of the protective film serves a protective structure attached to the sidewall of the step nearest to the substrate, and a first dielectric layer and a sacrificial layer nearest to the substrate are thus protected. The phenomenon thatthe first dielectric layer reacts with the substrate because of contact in the subsequent preparation process is avoided. Therefore, the phenomenon that a non-essential oxidation structure is formedin the substrate is avoided, and the performance of the finally formed 3D memory is improved.

Description

technical field [0001] The present application relates to the technical field of semiconductors, and more specifically, to a three-dimensional memory and a preparation method thereof. Background technique [0002] Memory is a memory device used to save information in modern information technology. With the increasing demand for integration and data storage density of various electronic devices, it is difficult for ordinary two-dimensional memory to further improve its integration and data storage density. Therefore, three-dimensional (3D) memory has emerged as the times require. [0003] Three-dimensional NAND (NAND) memory is a kind of three-dimensional flash memory. In its preparation process, a stacked structure is first deposited on the surface of a silicon substrate, and each stacked structure includes a multilayer interleaved first dielectric layer and a sacrificial layer, the sacrificial layer is located between adjacent first dielectric layers, refer to figure 1 , ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11578H01L27/11582H10B43/20H10B43/27
CPCH10B43/20H10B43/27
Inventor 赵治国霍宗亮李春龙叶甜春
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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