Verification method for branch instructions and branch prediction functions in speculation execution processor

Abstract

The invention provides a verification method for branch instructions and branch prediction functions in a speculation execution processor. The method includes the steps: S1 initializing drive and monitoring information; S2 judging whether the processor launches instruction fetching applications or not, executing S3 if the processor launches the instruction fetching applications, and executing S2 if not; S3 judging whether instruction fetching production line signals are effectively emptied or not, terminating operation if the signals are effectively emptied, returning the S2, and executing S4if not; S4 judging whether the instruction fetching production line signals are effectively paused or not, executing S4 if the signals are effectively paused, and executing S5 if not; S5 simulating instruction fetching cache logic of the processor, driving acquired random instructions on an instruction fetching logic interface of the processor, eliminating coupling relationships among instructionsand program counters, and setting corresponding instruction fetching signals into an effective state; S6 packaging and transmitting instruction information when instruction fetching signals are effective. According to the method, the branch instructions and the branch prediction functions of the speculation execution processor are sufficiently verified, and the utilization ratio and the testing efficiency of the random instructions are greatly improved.

Description

technical field [0001] The invention relates to the technical field of processor branch prediction, in particular to a method for verifying branch instructions and branch prediction functions in speculative execution processors. Background technique [0002] Branch prediction can affect the performance of the processor, and a high-accuracy branch predictor is a key component to improve the performance of the processor. Therefore, for speculative execution processors, the verification of branch instructions and branch prediction functions is becoming more and more important. [0003] In the prior art, verification of branch instructions and branch prediction functions is mainly performed in a processor-level verification environment. The processor verification environment mainly includes the processor to be tested, a reference model and a scoreboard. In the processor verification environment, instructions and data are stored in the same memory, and the processor fetches the...

AI Technical Summary

Problems solved by technology

First, the random test program is not executed sequentially. When there are many branch instructions in the random program, the random test program will jump and execute in the memory, resulting in a large number of random instructions not being executed, and the utilization rate of random instructions is low.

Second, random instructions are stored in the memory according to continuous addresses. Due to the existence of branch instructions, when the branch instruction jumps forward, the test program will form an infinite loop, resulting in insufficient random testing.

Through this technology, the problem of low utilization of random instructions can be solved; however, because branch instructions jump forward, an infinite loop will still be generated, resulting in insufficient testing of random branch instructions.

At the same time, this method also introduces other new problems: First, because the reference model and the processor under test are not executed synchronously, the reference model cannot obtain real-time events such as external interrupts, resulting in the instruction of both the reference model and the processor under test The flow will not match, causing the simulation to fail

Second, because in the prior art, instructions and data are in the same memory, if in the random process, memory access instructions may modify other random instructions that have been generated, causing random instructions to be lost

Therefore, the execution results of the reference model and the processor under test will be different, so that the processor under test cannot be verified normally.

[0010] To sum up, there are certain problems in the above two solutions, which cannot solve the problems of low utilization rate of random instructions and insufficient random testing at the same time.

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