Rapid-locking low-jitter clock data recovery circuit based on double loops

Abstract

The invention relates to a rapid-locking low-jitter clock data recovery circuit based on double loops, relates to the field of a microelectronic chip, and aims to solve the problem that an existing double-loop clock data recovery circuit cannot simultaneously have a high locking speed and small jitter. According to the invention, a band switching circuit, a multi-band VCO (Voltage Controlled Oscillator), a resistance voltage division circuit, an either-or circuit and a low-pass filter form a frequency-locked loop; the either-or circuit, the low-pass filter, the multi-band VCO, a BBPD (Bang-Bang type Phase Discriminator) and four charge pumps form a phase-locked loop; the band switching circuit is used for outputting a band control field and a loop selection signal according to an output clock clk0 of the multi-band VCO and a reference clock clk_ref; the resistance voltage division circuit is used for carrying out voltage division on a supply voltage vdd, and the voltage division outputend of the resistance voltage division circuit is connected with the frequency-locked loop input end of the either-or circuit; and the either-or circuit is used for gating the frequency-locked loop or the phase-locked loop according to the loop selection signal. The rapid-locking low-jitter clock data recovery circuit is applicable to clock data recovery.

Description

technical field [0001] The invention relates to the field of microelectronic chips, in particular to a clock data recovery circuit used in a serdes system. Background technique [0002] Clock data recovery circuit has been widely used in data communication and other fields. [0003] The clock data recovery circuit is mainly divided into the clock data recovery circuit based on the PLL structure and the clock data recovery circuit based on the PI structure, and the clock data recovery circuit based on the PLL structure can be further divided into a single loop and a double loop. The existing double-loop structure such as figure 1 As shown, the frequency-locked loop is composed of a phase frequency detector (PFD), a charge pump, a low-pass filter, a VCO and a two-choice circuit, and the phase-locked loop is composed of a voltage-controlled oscillator (VCO), a BBPD (Bang-Bang type phase detector), 4 charge pumps, a low-pass filter and an alternative circuit. The lock detectio...

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to solve the problem that the existing double-loop clock data recovery circuit cannot have fast locking speed and small jitter at the same time, thereby providing a clock data recovery circuit based on double-loop fast locking and low jitter

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